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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Toshiyuki Shibuya (Fujitsu Labs.)
Vice Chair Yusuke Matsunaga (Kyushu Univ.)
Secretary Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.)
Assistant Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric)

Conference Date Mon, Mar 2, 2015 13:00 - 16:35
Tue, Mar 3, 2015 08:50 - 16:40
Wed, Mar 4, 2015 08:50 - 14:40
Conference Place  
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Mon, Mar 2 PM 
13:00 - 14:40
(1) 13:00-13:25 A Fast Lithographic Mask Correction Algorithm VLD2014-153 Ahmd Awad, Atsushi Takahashi (Tokyo Institute of Technology)
(2) 13:25-13:50 A cut-pattern reduction method for routing in Self-Aligned Double Patterning VLD2014-154 Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)
(3) 13:50-14:15 Faster Numberlink solution using possibilities of topological routing VLD2014-155 Yuichiro Tanaka, Atsushi Takahashi (Tokyo Tech)
(4) 14:15-14:40 Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng VLD2014-156 Yuta Nakatani, Atsushi Takahashi (Tokyo Tech)
  14:40-14:55 Break ( 15 min. )
Mon, Mar 2 PM 
14:55 - 16:35
(5) 14:55-15:20 Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming VLD2014-157 Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)
(6) 15:20-15:45 Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing VLD2014-158 Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
(7) 15:45-16:10 Studies on Representation of Stacked Rectangular Dissections for 3D-LSI Floorplan VLD2014-159 Kazufumi Kogai, Kunihiro Fujiyoshi (TUAT)
(8) 16:10-16:35 A High Stability and Low Leakage Current Six-Transistor CMOS SRAM Employing a Single Low Supply Voltage VLD2014-160 Nobuaki Kobayashi, Ryusuke Ito, Koji Motojima, Tadayoshi Enomoto (Chuo Univ.)
Tue, Mar 3 AM 
08:50 - 10:05
(9) 08:50-09:15 A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture VLD2014-161 Song Bian, Michihiro Shintani (Kyoto Univ.), Zheng Wang (RWTH Aachen Univ.), Masayuki Hiromoto (Kyoto Univ.), Anupam Chattopadhyay (Nanyang Tech. Univ.), Takashi Sato (Kyoto Univ.)
(10) 09:15-09:40 A low-power soft error tolerant latch scheme VLD2014-162 Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)
(11) 09:40-10:05 Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI VLD2014-163 Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
  10:05-10:20 Break ( 15 min. )
Tue, Mar 3 AM 
10:20 - 12:00
(12) 10:20-10:45 ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths VLD2014-164 Junghoon Oh, Mineo Kaneko (JAIST)
(13) 10:45-11:10 Generation of Asynchronous Circuits from a High-level Synthesis Tool VLD2014-165 Taichi Komine, Hiroshi Saito (University of Aizu)
(14) 11:10-11:35 A design of FIR filters using High Level Synthesis
-- A automated design of FIR filters --
Ryo Yamamoto, Naoya Okada, Noriyuki Minegishi (MELCO)
(15) 11:35-12:00 A Virtual/Real Combined Verification Method for FPGAs VLD2014-167 Yoshimasa Ishino (MMS)
  12:00-13:20 Lunch Break ( 80 min. )
Tue, Mar 3 PM 
13:20 - 14:20
(16) 13:20-14:20 [Invited Talk]
Research in Industry and University for VLSI Design VLD2014-168
Satoshi Goto (Waseda Univ.)
  14:20-14:35 Break ( 15 min. )
Tue, Mar 3 PM 
14:35 - 16:40
(17) 14:35-15:00 [Memorial Lecture]
Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator VLD2014-169
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
(18) 15:00-15:25 [Memorial Lecture]
A Performance Enhanced Dual-switch Network-on-Chip Architecture VLD2014-170
Lian Zeng, Takahiro Watanabe (Waseda Univ.)
(19) 15:25-15:50 [Memorial Lecture]
A Length Matching Routing Method for Disordered Pins in PCB Design VLD2014-171
Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ.)
(20) 15:50-16:15 [Memorial Lecture]
Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design VLD2014-172
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.)
(21) 16:15-16:40 [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories VLD2014-173
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
Wed, Mar 4 AM 
08:50 - 10:05
(22) 08:50-09:15 Physical Unclonable Function Using RTN-Induced Time-Dependent Frequency Variance in Ring Oscillator VLD2014-174 Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
(23) 09:15-09:40 On PLL Layouts Evaluation based on Transistor-array Style VLD2014-175 Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)
(24) 09:40-10:05 Ground Bounce Suppressive Effect using Power Switch Driver to control Power Switch Rise Time VLD2014-176 Tetsutaro Ohnishi, Kimiyoshi Usami (S.I.T.)
  10:05-10:20 Break ( 15 min. )
Wed, Mar 4 AM 
10:20 - 12:00
(25) 10:20-10:45 Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design VLD2014-177 Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo)
(26) 10:45-11:10 LSI implementation of FEC for high-speed optical communication VLD2014-178 Koji Miyanohana, Susumu Hirano, Hideo Yoshida, Yoshikuni Miyata, Kenya Sugihara, Kazuo Kubo, Yoshiaki Konishi, Kiyoshi Onohara, Noriyuki Minegishi, Takashi Sugihara (Mitsubishi Elec.)
(27) 11:10-11:35 Energy minimization by voltage choice targeted for logic synthesis in silicon on thin buried oxide VLD2014-179 Jun Kawasaki, Kimiyoshi Usami (S.I.T.)
(28) 11:35-12:00 A parallel Algorithm for Realizing the Lax-Friedrichs Scheme in Computational Fluid Dynamics and its FPGA Implementation VLD2014-180 Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.)
  12:00-13:00 Lunch Break ( 60 min. )
Wed, Mar 4 PM 
13:00 - 14:40
(29) 13:00-13:25 An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework VLD2014-181 Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech)
(30) 13:25-13:50 A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists VLD2014-182 Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(31) 13:50-14:15 Implementation and evaluation of architecture using lookup table for approximate computing VLD2014-183 Shoichiro Sugiyama, tanvir ahmed, Yuko Hara-Azumi (Titech)
(32) 14:15-14:40 List-scheduling for tasks with execution time variation VLD2014-184 Komei Nomura, Yasuhiro Takashima (Univ. of Kitakyushu)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Noriyuki Minegishi (Mitsubishi Electric Corporation)
E-: giajbielectc
Tel: 0467-41-2944 
Announcement See also VLD's homepage:

Last modified: 2015-02-12 20:42:32

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