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=============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Kazutoshi Wakabayashi Secretary: Naoyuki Hoshi, Naohito Kojima, Kenshu Seto =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Akira Onozawa (NTT) Vice Chair: Kimiyoshi Usami (Shibaura Inst. of Tech.) Secretary: Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Akira Nagoya (Okayama Univ.) Vice Chair: Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.) Secretary: Yohei Hori (AIST), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Nobuya Watanabe (Okayama Univ.) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Shuichi Sakai (Univ. of Tokyo) Vice Chair: Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.) Secretary: Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC) Assistant: Hidetsugu Irie (Univ. of Electro-Comm.) DATE: Mon, Jan 17, 2011 10:10 - 17:40 Tue, Jan 18, 2011 09:00 - 17:25 PLACE: Hiyoshi Campus, Keio University(4-1-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8521, Japan. http://www.keio.ac.jp/ja/access/hiyoshi.html. Prof. Hideharu Amano) TOPICS: FPGA Applications, etc ---------------------------------------- Mon, Jan 17 AM (10:10 - 10:50) ---------------------------------------- (1)/CPSY 10:10 - 10:30 Behavior synthesis to hardware description language NSL of UML activity diagram Toshihiro Kamikage, Ryota Yamazaki, Naohiko Shimizu (Tokai Univ) (2)/CPSY 10:30 - 10:50 Implementation and evaluation of program development middleware for Cell Broadband Engine clusters Toshiaki Kamata, Akihiro Shitara, Yuri Nishikawa (Keio Univ.), Masato Yoshimi (Doshisha Univ.), Hideharu Amano (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 17 AM (11:05 - 12:25) ---------------------------------------- (3)/CPSY 11:05 - 11:25 Proposal and Preliminary Evaluation of System Diagnosis Technique for Large-scale Computer Network by Using Bayesian Network Shingo Harashima (Keio Univ.), Hitoshi Yabusaki (Hitachi.LTD), Wataru Sakamoto (Osaka Univ.), Hiroaki Nishi (Keio Univ.) (4)/CPSY 11:25 - 11:45 implementation of energy management sensor network and application to the home envirnment Yukio Suhara, Tomohisa Nakabe, Hiroaki Nishi (Keio Univ.) (5)/CPSY 11:45 - 12:05 Highly efficient mapping of electromagnetic wave interactions using the FDTD method for antenna designing on a CUDA-compatible GPU Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.) (6)/CPSY 12:05 - 12:25 Parallelization of the channel width search for FPGA routing Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto) ----- Break ( 65 min. ) ----- ---------------------------------------- Mon, Jan 17 PM (13:30 - 14:50) ---------------------------------------- (7)/VLD 13:30 - 13:50 Approximated Variable Scheduling for High-Level Synthesis Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.) (8)/VLD 13:50 - 14:10 A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) (9)/VLD 14:10 - 14:30 Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) (10)/VLD 14:30 - 14:50 Design and check a ROHM 0.18μm chip with Alliance VHDL toolset -- Trial the layout and netlist check tools -- Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 17 PM (15:05 - 16:25) ---------------------------------------- (11)/VLD 15:05 - 15:25 Acceleration of Regression Test of Compilers by Program Merging Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc) (12)/VLD 15:25 - 15:45 Automatic Retargeting of Binutils and GDB Based on Plug-in Method Soichiro Taga (Kwansei Gakuin Univ.), Takahiro Kumura (NEC/Osaka Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) (13)/VLD 15:45 - 16:05 Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.) (14)/VLD 16:05 - 16:25 Audio dynamic range compression using polynomial equations Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 17 PM (16:40 - 17:40) ---------------------------------------- (15) 16:40 - 17:00 (16) 17:00 - 17:20 (17) 17:20 - 17:40 ----- ----- ---------------------------------------- Tue, Jan 18 AM (09:00 - 10:40) ---------------------------------------- (18)/RECONF 09:00 - 09:20 A Regular Expression Matching Circuit Based on Decomposed Automaton Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) (19)/RECONF 09:20 - 09:40 Encoding Methods of Multiple Data Streams for Hardware Compressors of Floating-Point Data Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.) (20)/RECONF 09:40 - 10:00 FPGA implementation of human detectin with HOG features and AdaBoost Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) (21)/RECONF 10:00 - 10:20 A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems Tomonori Izumi (Ritsumeikan Univ.) (22)/RECONF 10:20 - 10:40 Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 18 AM (10:55 - 12:15) ---------------------------------------- (23)/RECONF 10:55 - 11:15 Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) (24)/RECONF 11:15 - 11:35 Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (25)/RECONF 11:35 - 11:55 A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (26)/RECONF 11:55 - 12:15 MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array Hironobu Morita, Minoru Watanabe (Shizuoka Univ.) ----- Break ( 75 min. ) ----- ---------------------------------------- Tue, Jan 18 PM (13:30 - 14:15) ---------------------------------------- (27)/RECONF 13:30 - 14:15 [Invited Talk] Design of Asynchronous Circuits with Bundled-data Implementation on FPGA Hiroshi Saito (Univ. Aizu) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 18 PM (14:30 - 15:50) ---------------------------------------- (28)/RECONF 14:30 - 14:50 Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) (29)/RECONF 14:50 - 15:10 Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) (30)/RECONF 15:10 - 15:30 Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) (31)/RECONF 15:30 - 15:50 A Consideration of Window Join Operator over Data Streams by using FPGA Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 18 PM (16:05 - 17:25) ---------------------------------------- (32)/RECONF 16:05 - 16:25 A Validation of FPGA-based Many-core Simulator ScalableCore System Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech) (33)/RECONF 16:25 - 16:45 Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA Naoki Fujieda, Kenji Kise (Tokyo Tech) (34)/RECONF 16:45 - 17:05 A Gateway and Remote Call Mechanisms for a PC-FPGA Hybrid Cluster Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.) (35)/RECONF 17:05 - 17:25 Design of Dataflow Machine on Multiple FPGAs Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) # Information for speakers General Talk will have 15 minutes for presentation and 5 minutes for discussion. === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Fri, Mar 18, 2011 - Sat, Mar 19, 2011: [Thu, Jan 20] # SECRETARY: Kenshu Seto (Tokyo City Univ.) E-mail: k    tcu http://www.sig-sldm.org/ === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Mar 2, 2011 - Fri, Mar 4, 2011: Okinawaken-Danjo-Kyodo-Sankaku Center [Fri, Dec 10], Topics: Design Technology for System-on-Silicon # SECRETARY: Akihisa Yamada (Sharp) E-mail:     a   s rp http://www.ieice.org/~vld/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Tomonori Izumi (Ritsumeikan Univ.) E-mail: t-i      iTEL&FAX: 077-561-2814 http://www.am.ics.keio.ac.jp/reconf/ === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Fri, Mar 18, 2011 - Sat, Mar 19, 2011: [Thu, Jan 20] Tue, Apr 12, 2011: [Fri, Feb 11] # SECRETARY: Hideharu Amano (Keio Univ.) E-mail: hun  ami  iohttp://www.ieice.org/iss/cpsy/jpn/ Last modified: 2010-12-20 17:29:17 |
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