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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Akira Onozawa (NTT)
Vice Chair Kimiyoshi Usami (Shibaura Inst. of Tech.)
Secretary Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Akira Nagoya (Okayama Univ.)
Vice Chair Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary Yohei Hori (AIST), Tomonori Izumi (Ritsumeikan Univ.)
Assistant Nobuya Watanabe (Okayama Univ.)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Shuichi Sakai (Univ. of Tokyo)
Vice Chair Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.)
Secretary Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC)
Assistant Hidetsugu Irie (Univ. of Electro-Comm.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Kazutoshi Wakabayashi
Secretary Naoyuki Hoshi, Naohito Kojima, Kenshu Seto

Conference Date Mon, Jan 17, 2011 10:10 - 17:40
Tue, Jan 18, 2011 09:00 - 17:25
Topics FPGA Applications, etc 
Conference Place Hiyoshi Campus, Keio University 
Address 4-1-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8521, Japan
Transportation Guide http://www.keio.ac.jp/ja/access/hiyoshi.html
Contact
Person
Prof. Hideharu Amano
Copyright
and
reproduction
以下の論文すべての著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Mon, Jan 17 AM 
10:10 - 10:50
(1)
CPSY
10:10-10:30 Behavior synthesis to hardware description language NSL of UML activity diagram VLD2010-84 CPSY2010-39 RECONF2010-53 Toshihiro Kamikage, Ryota Yamazaki, Naohiko Shimizu (Tokai Univ)
(2)
CPSY
10:30-10:50 Implementation and evaluation of program development middleware for Cell Broadband Engine clusters VLD2010-85 CPSY2010-40 RECONF2010-54 Toshiaki Kamata, Akihiro Shitara, Yuri Nishikawa (Keio Univ.), Masato Yoshimi (Doshisha Univ.), Hideharu Amano (Keio Univ.)
  10:50-11:05 Break ( 15 min. )
Mon, Jan 17 AM 
11:05 - 12:25
(3)
CPSY
11:05-11:25 Proposal and Preliminary Evaluation of System Diagnosis Technique for Large-scale Computer Network by Using Bayesian Network VLD2010-86 CPSY2010-41 RECONF2010-55 Shingo Harashima (Keio Univ.), Hitoshi Yabusaki (Hitachi.LTD), Wataru Sakamoto (Osaka Univ.), Hiroaki Nishi (Keio Univ.)
(4)
CPSY
11:25-11:45 implementation of energy management sensor network and application to the home envirnment VLD2010-87 CPSY2010-42 RECONF2010-56 Yukio Suhara, Tomohisa Nakabe, Hiroaki Nishi (Keio Univ.)
(5)
CPSY
11:45-12:05 Highly efficient mapping of electromagnetic wave interactions using the FDTD method for antenna designing on a CUDA-compatible GPU VLD2010-88 CPSY2010-43 RECONF2010-57 Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.)
(6)
CPSY
12:05-12:25 Parallelization of the channel width search for FPGA routing VLD2010-89 CPSY2010-44 RECONF2010-58 Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto)
  12:25-13:30 Break ( 65 min. )
Mon, Jan 17 PM 
13:30 - 14:50
(7)
VLD
13:30-13:50 Approximated Variable Scheduling for High-Level Synthesis VLD2010-90 CPSY2010-45 RECONF2010-59 Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.)
(8)
VLD
13:50-14:10 A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set VLD2010-91 CPSY2010-46 RECONF2010-60 Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
(9)
VLD
14:10-14:30 Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead VLD2010-92 CPSY2010-47 RECONF2010-61 Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute)
(10)
VLD
14:30-14:50 Design and check a ROHM 0.18μm chip with Alliance VHDL toolset
-- Trial the layout and netlist check tools --
VLD2010-93 CPSY2010-48 RECONF2010-62
Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.)
  14:50-15:05 Break ( 15 min. )
Mon, Jan 17 PM 
15:05 - 16:25
(11)
VLD
15:05-15:25 Acceleration of Regression Test of Compilers by Program Merging VLD2010-94 CPSY2010-49 RECONF2010-63 Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc)
(12)
VLD
15:25-15:45 Automatic Retargeting of Binutils and GDB Based on Plug-in Method VLD2010-95 CPSY2010-50 RECONF2010-64 Soichiro Taga (Kwansei Gakuin Univ.), Takahiro Kumura (NEC/Osaka Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
(13)
VLD
15:45-16:05 Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation VLD2010-96 CPSY2010-51 RECONF2010-65 Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(14)
VLD
16:05-16:25 Audio dynamic range compression using polynomial equations VLD2010-97 CPSY2010-52 RECONF2010-66 Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.)
  16:25-16:40 Break ( 15 min. )
Mon, Jan 17 PM 
16:40 - 17:40
(15) 16:40-17:00  
(16) 17:00-17:20  
(17) 17:20-17:40  
  -  
Tue, Jan 18 AM 
09:00 - 10:40
(18)
RECONF
09:00-09:20 A Regular Expression Matching Circuit Based on Decomposed Automaton VLD2010-98 CPSY2010-53 RECONF2010-67 Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)
(19)
RECONF
09:20-09:40 Encoding Methods of Multiple Data Streams for Hardware Compressors of Floating-Point Data VLD2010-99 CPSY2010-54 RECONF2010-68 Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.)
(20)
RECONF
09:40-10:00 FPGA implementation of human detectin with HOG features and AdaBoost VLD2010-100 CPSY2010-55 RECONF2010-69 Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
(21)
RECONF
10:00-10:20 A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems VLD2010-101 CPSY2010-56 RECONF2010-70 Tomonori Izumi (Ritsumeikan Univ.)
(22)
RECONF
10:20-10:40 Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration VLD2010-102 CPSY2010-57 RECONF2010-71 Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.)
  10:40-10:55 Break ( 15 min. )
Tue, Jan 18 AM 
10:55 - 12:15
(23)
RECONF
10:55-11:15 Feasibility of JHDL for Dynamically Reconfigurable Hardware Design VLD2010-103 CPSY2010-58 RECONF2010-72 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)
(24)
RECONF
11:15-11:35 Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs VLD2010-104 CPSY2010-59 RECONF2010-73 Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(25)
RECONF
11:35-11:55 A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology VLD2010-105 CPSY2010-60 RECONF2010-74 Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(26)
RECONF
11:55-12:15 MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array VLD2010-106 CPSY2010-61 RECONF2010-75 Hironobu Morita, Minoru Watanabe (Shizuoka Univ.)
  12:15-13:30 Break ( 75 min. )
Tue, Jan 18 PM 
13:30 - 14:15
(27)
RECONF
13:30-14:15 [Invited Talk]
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA VLD2010-107 CPSY2010-62 RECONF2010-76
Hiroshi Saito (Univ. Aizu)
  14:15-14:30 Break ( 15 min. )
Tue, Jan 18 PM 
14:30 - 15:50
(28)
RECONF
14:30-14:50 Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator VLD2010-108 CPSY2010-63 RECONF2010-77 Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.)
(29)
RECONF
14:50-15:10 Silent Large Datapath : A Ultra Low Power Accelarater VLD2010-109 CPSY2010-64 RECONF2010-78 Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications)
(30)
RECONF
15:10-15:30 Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater VLD2010-110 CPSY2010-65 RECONF2010-79 Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications)
(31)
RECONF
15:30-15:50 A Consideration of Window Join Operator over Data Streams by using FPGA VLD2010-111 CPSY2010-66 RECONF2010-80 Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC)
  15:50-16:05 Break ( 15 min. )
Tue, Jan 18 PM 
16:05 - 17:25
(32)
RECONF
16:05-16:25 A Validation of FPGA-based Many-core Simulator ScalableCore System VLD2010-112 CPSY2010-67 RECONF2010-81 Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech)
(33)
RECONF
16:25-16:45 Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA VLD2010-113 CPSY2010-68 RECONF2010-82 Naoki Fujieda, Kenji Kise (Tokyo Tech)
(34)
RECONF
16:45-17:05 A Gateway and Remote Call Mechanisms for a PC-FPGA Hybrid Cluster VLD2010-114 CPSY2010-69 RECONF2010-83 Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.)
(35)
RECONF
17:05-17:25 Design of Dataflow Machine on Multiple FPGAs VLD2010-115 CPSY2010-70 RECONF2010-84 Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)

Announcement for Speakers
General TalkEach speech will have 15 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Akihisa Yamada (Sharp)
E-: asrp
http://www.ieice.org/~vld/ 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Tomonori Izumi (Ritsumeikan Univ.)
E-: t-ii
TEL&FAX: 077-561-2814
http://www.am.ics.keio.ac.jp/reconf/ 
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Hideharu Amano (Keio Univ.)
E-: hunamiio
http://www.ieice.org/iss/cpsy/jpn/ 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kenshu Seto (Tokyo City Univ.)
E-: ktcu
http://www.sig-sldm.org/ 


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