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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kazutoshi Wakabayashi (NEC)
Vice Chair Atsushi Takahashi (Tokyo Inst. of Tech.)
Secretary Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Shinji Kimura
Secretary Takashi Aoki, Naoyuki Hoshi, Kenshu Seto

Conference Date Wed, May 20, 2009 14:30 - 16:50
Thu, May 21, 2009 10:00 - 11:55
Topics System Design, etc. 
Conference Place Kitakyushu International Conference Center 
Transportation Guide
Prof. Yasuhiro Takashima
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, May 20 PM  System-level Design
Chair: Nozomu Togawa (Waseda Univ.)
14:30 - 15:45
14:30-14:55 Task Migration for Energy Savings in Multiprocessor Real-Time Systems VLD2009-1 Gang Zeng (Nagoya Univ.), Shinpei Kato (The Univ. of Tokyo), Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
14:55-15:20 A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations VLD2009-2 Tomoaki Hara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Printing Corp.)
15:20-15:45 A scan test generation method to reduce the number of detected untestable faults VLD2009-3 Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.)
  15:45-16:00 Break ( 15 min. )
Wed, May 20 PM  Optimizing Algorithms
16:00 - 16:50
(4) 16:00-16:25  
(5) 16:25-16:50  
Thu, May 21 AM  Physical Design
Chair: Ichiro Kohno (Renesas Technology Corp.)
10:00 - 10:50
10:00-10:25 A RST Construction Method for Vertices with Maximum Path Length VLD2009-4 Masafumi Inoue, Yoichi Tomioka (Tokyo Inst. of Tech.), Yukihide Kohira (the Univ. of Aizu), Atsushi Takahashi (Osaka Univ.)
10:25-10:50 Importance sampling with two-phase preprocess considering structural symmetry of SRAM circuits VLD2009-5 Takanori Date, Shiho Hagiwara, Takumi Uezono (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.), Kazuya Masu (Tokyo Inst. of Tech.)
  10:50-11:05 Break ( 15 min. )
Thu, May 21 PM  Low Power Design
11:05 - 11:55
(8) 11:05-11:30  
(9) 11:30-11:55  

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Ichiro Kohno (Renesas Technology Corp.)
E-: his
TEL: +81-42-312-5873 
Announcement See also VLD's homepage:
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  

Last modified: 2009-05-12 18:11:43

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