Tue, Mar 1 AM
09:30 - 10:45 |
| (1) |
09:30-09:55 |
Design of Successive Approximation ADC using Standard Cell Design Flow |
Hiroshi Hirano, Satoshi Komatsu (Tokyo Denki Univ.) |
| (2) |
09:55-10:20 |
Multi-process Automatic Generation System for ADC Using Standard cell |
Takumi Fukushima, Satoshi Komatsu (Tokyo Denki Univ.) |
| (3) |
10:20-10:45 |
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10:45-10:55 |
Break ( 10 min. ) |
Tue, Mar 1 AM
10:55 - 11:45 |
| (4) |
10:55-11:20 |
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement |
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) |
| (5) |
11:20-11:45 |
Applicability Evaluation of the Delay Testable Circuit to PUF |
Eisuke Ohama, Haruka Chino, Hiroyuki Yotuyanagi, Masaki Hashizume (Tokushima Univ.) |
| |
11:45-12:55 |
Break ( 70 min. ) |
Tue, Mar 1 PM
12:55 - 14:10 |
| (6) |
12:55-13:20 |
A TMR-Based Approximate Corrector for Fail-Operational Systems |
Mitsuyoshi Ashida, Tomoo Inoue, Hideyuki Ichihara (City Univ) |
| (7) |
13:20-13:45 |
Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing |
Koji Makino, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
| (8) |
13:45-14:10 |
A Logic Locking Method based on SFLL-hd at Register Transfer Level |
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) |
| |
14:10-14:20 |
Break ( 10 min. ) |
Tue, Mar 1 PM
14:20 - 15:35 |
| (9) |
14:20-14:45 |
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability |
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) |
| (10) |
14:45-15:10 |
SAT-based LFSR Seed Generation for Delay Fault BIST |
Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) |
| (11) |
15:10-15:35 |
State assignment method to improve transition fault coverage for controllers including invalid states |
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) |
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15:35-15:45 |
Break ( 10 min. ) |
Tue, Mar 1 PM
15:45 - 17:00 |
| (12) |
15:45-16:10 |
Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault |
Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ) |
| (13) |
16:10-16:35 |
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information |
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.) |
| (14) |
16:35-17:00 |
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