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Paper Abstract and Keywords
Presentation
[Invited Talk] Instruction Set Architecture for Extended Hamming Code with Small Energy Consumption
Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Energy reduction of error control of wireless communication is indispensable to tiny embedded systems powered by small batteries. In order to achieve this goal, an error check and correction (ECC) system that can flexibly change its robustness while keeping high encoding rate is required. This paper proposes an instruction set architecture that processes extended Hamming code efficiently. Experimental results show that the proposed instruction set architecture reduces 68 - 80% energy consumption compared to RISC software implementation of ECC system for extended Hamming code.
Keyword (in Japanese) (See Japanese page) 
(in English) ASIP / Low Energy / Communication Quality / ECC / Extended Hamming Code / / /  
Reference Info. IEICE Tech. Rep.
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Conference Information
Committee MW  
Conference Date 2012-08-08 - 2012-08-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Chulalongkorn University, Bangkok, Thailand 
Topics (in Japanese) (See Japanese page) 
Topics (in English) RF, Microwave, and Millimeter-wave Theory and Techniques 
Paper Information
Registration To MW 
Conference Code 2012-08-MW 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Instruction Set Architecture for Extended Hamming Code with Small Energy Consumption 
Sub Title (in English)  
Keyword(1) ASIP  
Keyword(2) Low Energy  
Keyword(3) Communication Quality  
Keyword(4) ECC  
Keyword(5) Extended Hamming Code  
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1st Author's Name Takashi Hamabe  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Yoshinori Takeuchi  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Masaharu Imai  
3rd Author's Affiliation Osaka University (Osaka Univ.)
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