Paper Abstract and Keywords |
Presentation |
2022-03-10 10:30
A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. Test compaction methods have been proposed to reduce the number of test patterns. However, Test compaction methods might not be able to reduce many test patterns due to the circuit structures. Also, design-for-testability methods to change circuit structures such that test compaction is efficiently applied have been proposed. However, when a design-for-testability method is applied at gate level, the optimal timing by logic synthesis might be lost due the delay increasing. It is important to apply design-for-testability considering concurrent testing at register transfer level before application of logic synthesis. Conventional controller augmentation methods considering concurrent testing at register transfer level design state transitions on invalid states. Since the number of status registers increases by the controller augmentation, the area overhead becomes larger. In this paper, we focus on don't cares in control signal values supplied when the state transitions on valid states are performed, and propose a don't care filling method of the control signals to reduce the number of test patterns while suppressing the area overhead. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
control signals / don't care filling / concurrent test / data-paths / pseudo boolean optimization / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 426, DC2021-90, pp. 67-72, March 2022. |
Paper # |
DC2021-90 |
Date of Issue |
2022-03-03 (CPSY, DC) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2021-56 DC2021-90 |
Conference Information |
Committee |
CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC |
Conference Date |
2022-03-10 - 2022-03-11 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
ETNET2021 |
Paper Information |
Registration To |
DC |
Conference Code |
2022-03-CPSY-DC-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing |
Sub Title (in English) |
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Keyword(1) |
control signals |
Keyword(2) |
don't care filling |
Keyword(3) |
concurrent test |
Keyword(4) |
data-paths |
Keyword(5) |
pseudo boolean optimization |
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1st Author's Name |
Haofeng Xu |
1st Author's Affiliation |
Nihon University (Nihon Univ) |
2nd Author's Name |
Toshinori Hosokawa |
2nd Author's Affiliation |
Nihon University (Nihon Univ) |
3rd Author's Name |
Hiroshi Yamazaki |
3rd Author's Affiliation |
Nihon University (Nihon Univ) |
4th Author's Name |
Masayuki Arai |
4th Author's Affiliation |
Nihon University (Nihon Univ) |
5th Author's Name |
Masayoshi Yoshimura |
5th Author's Affiliation |
Kyoto Sangyo University (KSU) |
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Speaker |
Author-1 |
Date Time |
2022-03-10 10:30:00 |
Presentation Time |
20 minutes |
Registration for |
DC |
Paper # |
CPSY2021-56, DC2021-90 |
Volume (vol) |
vol.121 |
Number (no) |
no.425(CPSY), no.426(DC) |
Page |
pp.67-72 |
#Pages |
6 |
Date of Issue |
2022-03-03 (CPSY, DC) |
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