IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2022-03-10 10:30
A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing
Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. Test compaction methods have been proposed to reduce the number of test patterns. However, Test compaction methods might not be able to reduce many test patterns due to the circuit structures. Also, design-for-testability methods to change circuit structures such that test compaction is efficiently applied have been proposed. However, when a design-for-testability method is applied at gate level, the optimal timing by logic synthesis might be lost due the delay increasing. It is important to apply design-for-testability considering concurrent testing at register transfer level before application of logic synthesis. Conventional controller augmentation methods considering concurrent testing at register transfer level design state transitions on invalid states. Since the number of status registers increases by the controller augmentation, the area overhead becomes larger. In this paper, we focus on don't cares in control signal values supplied when the state transitions on valid states are performed, and propose a don't care filling method of the control signals to reduce the number of test patterns while suppressing the area overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) control signals / don't care filling / concurrent test / data-paths / pseudo boolean optimization / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 426, DC2021-90, pp. 67-72, March 2022.
Paper # DC2021-90 
Date of Issue 2022-03-03 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2021-56 DC2021-90

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2022-03-10 - 2022-03-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2021 
Paper Information
Registration To DC 
Conference Code 2022-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing 
Sub Title (in English)  
Keyword(1) control signals  
Keyword(2) don't care filling  
Keyword(3) concurrent test  
Keyword(4) data-paths  
Keyword(5) pseudo boolean optimization  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Haofeng Xu  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Hiroshi Yamazaki  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Masayuki Arai  
4th Author's Affiliation Nihon University (Nihon Univ)
5th Author's Name Masayoshi Yoshimura  
5th Author's Affiliation Kyoto Sangyo University (KSU)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2022-03-10 10:30:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # CPSY2021-56, DC2021-90 
Volume (vol) vol.121 
Number (no) no.425(CPSY), no.426(DC) 
Page pp.67-72 
#Pages
Date of Issue 2022-03-03 (CPSY, DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan