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| Paper Abstract and Keywords | ||
| Presentation | 2022-02-22 14:25 Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction Kohei Shinyamada, Akira Yamawaki (Kyutech)  ITS2021-61 IE2021-70 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real camera. The hardware was developed using high-level synthesis. We evaluated the performance of the developed hardware alone, and found that the performance was 166 fps for the image size QVGA and the number of time-series images N=4. The hardware processing was superior in terms of power efficiency when compared to the embedded CPU. However, since the frame rate of the camera used in the prototype was approximately 12 fps, the maximum frame rate of the entire system was approximately 12 fps. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / High-Level Synthesis / HLS / Image Processing / Real Camera System / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 374, IE2021-70, pp. 214-218, Feb. 2022. | |
| Paper # | IE2021-70 | |
| Date of Issue | 2022-02-14 (ITS, IE) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ITS2021-61 IE2021-70 |
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| Conference Information | |
| Committee | IE ITS ITE-AIT ITE-ME ITE-MMS |
| Conference Date | 2022-02-21 - 2022-02-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Image Processing, etc. |
| Paper Information | |
| Registration To | IE |
| Conference Code | 2022-02-IE-ITS-AIT-ME-MMS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | High-Level Synthesis |
| Keyword(3) | HLS |
| Keyword(4) | Image Processing |
| Keyword(5) | Real Camera System |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kohei Shinyamada |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
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| Speaker | Author-1 |
| Date Time | 2022-02-22 14:25:00 |
| Presentation Time | 15 minutes |
| Registration for | IE |
| Paper # | ITS2021-61, IE2021-70 |
| Volume (vol) | vol.121 |
| Number (no) | no.373(ITS), no.374(IE) |
| Page | pp.214-218 |
| #Pages | 5 |
| Date of Issue | 2022-02-14 (ITS, IE) |
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