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| Paper Abstract and Keywords | ||
| Presentation | 2022-01-25 10:45 An Implementation of a Real-time Stereo Matching System on FPGA Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.)  VLD2021-65 CPSY2021-34 RECONF2021-73 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | To make full use of stereo data in autonomous driving system, the techniques to generate depth-map in real-time are necessary for the users. Semi-Global Matching(SGM) has been widely accepted to derive depth information in the field of computer vision. Generally, GPU is always an acceptable choice to meet the requirements of real-time. However, the high energy and resource consumption on GPU brings a burden on edge devices. Thus, FPGA has been a promising platform for its benefit of energy efficiency and high-speed performance. With considering the maintenance, we choose Vitis HLS 2020.1 as our tool and achieve 45.45 fps on the input source of 1920 x 1080, which is 1.28x faster than the performance on GPU Tegra X2. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Stereo matching / SGM / AXI Streaming / Slide window / Vitis HLS / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-73, pp. 90-95, Jan. 2022. | |
| Paper # | RECONF2021-73 | |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-65 CPSY2021-34 RECONF2021-73 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM |
| Conference Date | 2022-01-24 - 2022-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2022-01-RECONF-VLD-CPSY-ARC-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Implementation of a Real-time Stereo Matching System on FPGA |
| Sub Title (in English) | |
| Keyword(1) | Stereo matching |
| Keyword(2) | SGM |
| Keyword(3) | AXI Streaming |
| Keyword(4) | Slide window |
| Keyword(5) | Vitis HLS |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kaijie Wei |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Yuki Kuno |
| 2nd Author's Affiliation | Marelli Corporation (Marelli Corp.) |
| 3rd Author's Name | Masatoshi Arai |
| 3rd Author's Affiliation | Saitama University (Saitama Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2022-01-25 10:45:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2021-65, CPSY2021-34, RECONF2021-73 |
| Volume (vol) | vol.121 |
| Number (no) | no.342(VLD), no.343(CPSY), no.344(RECONF) |
| Page | pp.90-95 |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
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