Paper Abstract and Keywords |
Presentation |
2022-01-20 11:30
FPGA implementation and evaluation of Ternary sparse XNOR-Net and Proposal of Ternary sparse Net without XNOR Taichi Megumi, Takayuki Kawahara (Tokyo Univ of Science) CAS2021-55 ICTSSL2021-32 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Ternary Sparse XNOR-Net is a method to suppress decline of recognition accuracy by ternarizing the weights of the neural network to (-1,0,1), and to reduce the circuit size by not wiring the weight 0 part. The activation value is binarized to (-1,1), and the multiplication between (-1,1) is replaced by XNOR. In this study, we implemented a three-layer Ternary Sparse XNOR-Net on FPGA and evaluate it by MNIST inference. As a result, the recognition rate was improved by 3.6% compared with Binarized Neural Network, and the LUT usage rate of FPGA was reduced by 76.78%. As a further circuit size reduction idea, we proposed Ternary Sparse Net, where the multiplication circuit is replaced by a simple wiring and inverter instead of XNOR. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Neural Network / Deep Learning / FPGA / Ternary / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 325, CAS2021-55, pp. 19-23, Jan. 2022. |
Paper # |
CAS2021-55 |
Date of Issue |
2022-01-13 (CAS, ICTSSL) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2021-55 ICTSSL2021-32 |
Conference Information |
Committee |
ICTSSL CAS |
Conference Date |
2022-01-20 - 2022-01-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CAS |
Conference Code |
2022-01-ICTSSL-CAS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
FPGA implementation and evaluation of Ternary sparse XNOR-Net and Proposal of Ternary sparse Net without XNOR |
Sub Title (in English) |
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Neural Network |
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Deep Learning |
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FPGA |
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Ternary |
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1st Author's Name |
Taichi Megumi |
1st Author's Affiliation |
Tokyo University of Science (Tokyo Univ of Science) |
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Takayuki Kawahara |
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Tokyo University of Science (Tokyo Univ of Science) |
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Speaker |
Author-1 |
Date Time |
2022-01-20 11:30:00 |
Presentation Time |
20 minutes |
Registration for |
CAS |
Paper # |
CAS2021-55, ICTSSL2021-32 |
Volume (vol) |
vol.121 |
Number (no) |
no.325(CAS), no.326(ICTSSL) |
Page |
pp.19-23 |
#Pages |
5 |
Date of Issue |
2022-01-13 (CAS, ICTSSL) |
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