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Paper Abstract and Keywords
Presentation 2021-12-01 10:35
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 Link to ES Tech. Rep. Archives: ICD2021-30
Abstract (in Japanese) (See Japanese page) 
(in English) IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance for battery-driven devices has been increasing. Many IoT applications requires edge-devices to operate intermittently at a high frequent manner yet exhausting leakage power even on standby period. Newly proposed non-volatile cool mega array with multi-context (NVCMA/MC) — one of low-power oriented coarse-grained reconfigurable accelerators — has a non-volatile flip-flop (NVFF) with magnetic tunnel junction (MTJ) and supports power gating (PG) to reduce leakage power efficiently. NVCMA/MC is an extended version of the conventional NVCMA and facilitates the optimization of the trade-off between power and performance by enlarging the processing element (PE) array and inserting pipeline registers between each row of the PE. Newly added multi-context memories which perform task-level reconfiguration can take advantage of NVFF by efficient runtime PG. Evaluation of real chips implemented with 40nm MTJ/MOS hybrid process technology demonstrates that 65% of store energy is reduced by dividing store operation into two steps — 35 ns of short store and 140 ns of long store. With multi-context power gating, we also found that applications that run intermittently for intervals as short as around 3μs can benefit from the PG effect.
Keyword (in Japanese) (See Japanese page) 
(in English) CGRA / coarse-grained reconfigurable architecture / nonvolatile memory / magnetic tunnel junction / power gating / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 277, VLD2021-20, pp. 19-24, Dec. 2021.
Paper # VLD2021-20 
Date of Issue 2021-11-24 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 Link to ES Tech. Rep. Archives: ICD2021-30

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2021-12-01 - 2021-12-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2021 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2021-12-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops 
Sub Title (in English)  
Keyword(1) CGRA  
Keyword(2) coarse-grained reconfigurable architecture  
Keyword(3) nonvolatile memory  
Keyword(4) magnetic tunnel junction  
Keyword(5) power gating  
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1st Author's Name Aika Kamei  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takuya Kojima  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Hideharu Amano  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Daiki Yokoyama  
4th Author's Affiliation Shibaura Institute of Technology (SIT)
5th Author's Name Hisato Miyauchi  
5th Author's Affiliation Shibaura Institute of Technology (SIT)
6th Author's Name Kimiyoshi Usami  
6th Author's Affiliation Shibaura Institute of Technology (SIT)
7th Author's Name Keizo Hiraga  
7th Author's Affiliation Sony Semiconductor Solutions (SSS)
8th Author's Name Kenta Suzuki  
8th Author's Affiliation Sony Semiconductor Solutions (SSS)
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Speaker Author-1 
Date Time 2021-12-01 10:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2021-20, ICD2021-30, DC2021-26, RECONF2021-28 
Volume (vol) vol.121 
Number (no) no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) 
Page pp.19-24 
#Pages
Date of Issue 2021-11-24 (VLD, ICD, DC, RECONF) 


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