Paper Abstract and Keywords |
Presentation |
2021-12-01 14:20
A Dual-mode SAR ADC to Detect Power Analysis Attack Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.) VLD2021-30 ICD2021-40 DC2021-36 RECONF2021-38 Link to ES Tech. Rep. Archives: ICD2021-40 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Distributed IoT devices are exposed to unexpected interferences by physical accesses by malicious attackers. An on-chip noise monitor using a dual-mode ADC is developed to detect the insertion of off-chip components as malicious attempts of power noise measurement attacks. Fabricated in 65 nm CMOS, the on-chip noise monitor is examined for the detectability of series resistor, parallel capacitors and voltage probe that are intentionally inserted on power lines. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
power supply noise / side channel attack / power noise attack / electromagnetic noise attack / digital integrated circuit / on-chip noise monitor / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 278, ICD2021-40, pp. 78-82, Dec. 2021. |
Paper # |
ICD2021-40 |
Date of Issue |
2021-11-24 (VLD, ICD, DC, RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2021-30 ICD2021-40 DC2021-36 RECONF2021-38 Link to ES Tech. Rep. Archives: ICD2021-40 |
Conference Information |
Committee |
VLD DC RECONF ICD IPSJ-SLDM |
Conference Date |
2021-12-01 - 2021-12-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2021 -New Field of VLSI Design- |
Paper Information |
Registration To |
ICD |
Conference Code |
2021-12-VLD-DC-RECONF-ICD-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Dual-mode SAR ADC to Detect Power Analysis Attack |
Sub Title (in English) |
|
Keyword(1) |
power supply noise |
Keyword(2) |
side channel attack |
Keyword(3) |
power noise attack |
Keyword(4) |
electromagnetic noise attack |
Keyword(5) |
digital integrated circuit |
Keyword(6) |
on-chip noise monitor |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Takuya Wadatsumi |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Takuji Miki |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Makoto Nagata |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2021-12-01 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
VLD2021-30, ICD2021-40, DC2021-36, RECONF2021-38 |
Volume (vol) |
vol.121 |
Number (no) |
no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) |
Page |
pp.78-82 |
#Pages |
5 |
Date of Issue |
2021-11-24 (VLD, ICD, DC, RECONF) |
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