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Paper Abstract and Keywords
Presentation 2021-03-26 09:40
Prototyping of A Packet Aggregation/Disaggregation Router with FPGA
Shiro Takayama, Naoki Fujieda, Michihiro Aoki (Aichi Inst. of Tech.) CPSY2020-58 DC2020-88
Abstract (in Japanese) (See Japanese page) 
(in English) Network traffic volume is increasing due to the growth of IoT services. In particular, increase of short packets may affect the packet processing performance of routers. One of the methods to reduce the number of packets on the network is called packet aggregation, where a router reconstructs many short packets into an aggregated packet, and vice versa. In this article, we report the results of our hardware prototyping of packet aggregation/disaggregation router using NetFPGA, a platform for network hardware development that includes an FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Packet aggregation / Short packet / NetFPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 435, CPSY2020-58, pp. 49-54, March 2021.
Paper # CPSY2020-58 
Date of Issue 2021-03-18 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2020-58 DC2020-88

Conference Information
Conference Date 2021-03-25 - 2021-03-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2021 
Paper Information
Registration To CPSY 
Conference Code 2021-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Prototyping of A Packet Aggregation/Disaggregation Router with FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Packet aggregation  
Keyword(3) Short packet  
Keyword(4) NetFPGA  
1st Author's Name Shiro Takayama  
1st Author's Affiliation Aichi Institute of Technology (Aichi Inst. of Tech.)
2nd Author's Name Naoki Fujieda  
2nd Author's Affiliation Aichi Institute of Technology (Aichi Inst. of Tech.)
3rd Author's Name Michihiro Aoki  
3rd Author's Affiliation Aichi Institute of Technology (Aichi Inst. of Tech.)
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Date Time 2021-03-26 09:40:00 
Presentation Time 20 
Registration for CPSY 
Paper # IEICE-CPSY2020-58,IEICE-DC2020-88 
Volume (vol) IEICE-120 
Number (no) no.435(CPSY), no.436(DC) 
Page pp.49-54 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2021-03-18,IEICE-DC-2021-03-18 

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