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Paper Abstract and Keywords
Presentation 2021-03-26 11:00
An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91
Abstract (in Japanese) (See Japanese page) 
(in English) Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis method for a single universal logical fault model using multi-cycle capture test sets was proposed for scan design circuits. However, the problem remains that the fault diagnosis method does not estimate types of defects corresponding to suspected faults. In this paper, we propose an estimation method of defect types using neural networks with the features represent the major logical fault models such as stuck-at 0 fault, stuck-at 1 fault, dominant bridging fault, and open fault.
Keyword (in Japanese) (See Japanese page) 
(in English) universal logical fault model / fault diagnosis / multi-cycle capture testing / artificial neural networks / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 436, DC2020-91, pp. 67-72, March 2021.
Paper # DC2020-91 
Date of Issue 2021-03-18 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2021-03-25 - 2021-03-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2021 
Paper Information
Registration To DC 
Conference Code 2021-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks 
Sub Title (in English)  
Keyword(1) universal logical fault model  
Keyword(2) fault diagnosis  
Keyword(3) multi-cycle capture testing  
Keyword(4) artificial neural networks  
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1st Author's Name Natsuki Ota  
1st Author's Affiliation Nihon Univercity (Nihon Univ.)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon Univercity (Nihon Univ.)
3rd Author's Name Koji Yamazaki  
3rd Author's Affiliation Meiji Univercity (Meiji Univ.)
4th Author's Name Yukari Yamauchi  
4th Author's Affiliation Nihon Univercity (Nihon Univ.)
5th Author's Name Masayuki Arai  
5th Author's Affiliation Nihon Univercity (Nihon Univ.)
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Speaker
Date Time 2021-03-26 11:00:00 
Presentation Time 20 
Registration for DC 
Paper # IEICE-CPSY2020-61,IEICE-DC2020-91 
Volume (vol) IEICE-120 
Number (no) no.435(CPSY), no.436(DC) 
Page pp.67-72 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2021-03-18,IEICE-DC-2021-03-18 


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