| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2021-03-26 12:00 A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)  CPSY2020-64 DC2020-94 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. However, with conventional logic locking methods, the correct key can be easily decrypted by a SAT attack. Therefore, anti-SAT methods, which are logic locking method that is resistant to SAT attacks, have been proposed. However, it is difficult to design logic locking based on anti-SAT into logic circuits at gate level. In this paper, we propose a logic locking method based on anti-SAT at register transfer level. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Logic Locking / Register Transfer Level / SAT Attack / Anti-SAT / design for security / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 436, DC2020-94, pp. 85-90, March 2021. | |
| Paper # | DC2020-94 | |
| Date of Issue | 2021-03-18 (CPSY, DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2020-64 DC2020-94 |
|
| Conference Information | |
| Committee | CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC |
| Conference Date | 2021-03-25 - 2021-03-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2021 |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2021-03-CPSY-DC-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Logic Locking Method Based on Anti-SAT at Register Transfer Level |
| Sub Title (in English) | |
| Keyword(1) | Logic Locking |
| Keyword(2) | Register Transfer Level |
| Keyword(3) | SAT Attack |
| Keyword(4) | Anti-SAT |
| Keyword(5) | design for security |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Atsuya Tsujikawa |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University (Kyoto Sangyo Univ.) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2021-03-26 12:00:00 |
| Presentation Time | 20 minutes |
| Registration for | DC |
| Paper # | CPSY2020-64, DC2020-94 |
| Volume (vol) | vol.120 |
| Number (no) | no.435(CPSY), no.436(DC) |
| Page | pp.85-90 |
| #Pages | 6 |
| Date of Issue | 2021-03-18 (CPSY, DC) |
[Return to Top Page]