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Paper Abstract and Keywords
Presentation 2021-03-04 13:25
A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design
Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The latest memory protection function provided by Intel SGX is realized by constructing a tree structure (authentication tree) using Message Authentication Code (MAC) and Authentication Encryption (AE). However, the authentication tree used in SGX (SGX Integrity Tree: SIT) is designed with MAC and AE based on block ciphers under the condition that the protected memory area is at most 96 MB, which leads to the limitation of scalability and latency in verification/update of memory data. Addressing the scalability and latency issues, this paper proposes a new authentication tree using MAC and AE based on TBC that has a public parameter called Tweak in addition to input. We first describe the new TBC-based MAC and AE used in the proposed authentication tree, and then present the hardware architecture that can support various authentication tree parameters (i.e., the memory size to be protected and the number of branches). The hardware performance is evaluated by logic synthesis in comparison with the corresponding SIT hardware. The evaluation results show that the proposed authentication tree can verify and update data with smaller latency than SIT as the protected memory size increases. For example, for the case that the protected memory size is 1 GByte, the proposed authentication tree can reduce the data validation time and data update time to 60.9% and 25.0% in comparison with SIT, respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) memory security / tweakable block cipher / authentication tree / hardware architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 401, HWS2020-58, pp. 85-90, March 2021.
Paper # HWS2020-58 
Date of Issue 2021-02-24 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-83 HWS2020-58

Conference Information
Committee HWS VLD  
Conference Date 2021-03-03 - 2021-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2021-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design 
Sub Title (in English)  
Keyword(1) memory security  
Keyword(2) tweakable block cipher  
Keyword(3) authentication tree  
Keyword(4) hardware architecture  
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1st Author's Name Maya Oda  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Rei Ueno  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Naofumi Homma  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Akiko Inoue  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Kazuhiko Minematsu  
5th Author's Affiliation NEC Corporation (NEC)
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Speaker
Date Time 2021-03-04 13:25:00 
Presentation Time 25 
Registration for HWS 
Paper # IEICE-VLD2020-83,IEICE-HWS2020-58 
Volume (vol) IEICE-120 
Number (no) no.400(VLD), no.401(HWS) 
Page pp.85-90 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2021-02-24,IEICE-HWS-2021-02-24 


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