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| Presentation | 2021-03-03 13:50 [Memorial Lecture] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita (Ritsumeikan University)  VLD2020-73 HWS2020-48 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We usually use {it Mixed-Polarity Multiple-Control Toffoli (MPMCT)} gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert {it SWAP} gates such that all the gates can be performed on {it Nearest Neighbor Architectures (NNAs).} Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered {it dynamically} as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when decomposing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Quantum Circuit / Mixed-Polarity Multiple-Control Toffoli (MPMCT) gate / Nearest Neighbor Architecture (NNA) / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 400, VLD2020-73, pp. 31-31, March 2021. | |
| Paper # | VLD2020-73 | |
| Date of Issue | 2021-02-24 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-73 HWS2020-48 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2021-03-03 - 2021-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2021-03-HWS-VLD |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures |
| Sub Title (in English) | |
| Keyword(1) | Quantum Circuit |
| Keyword(2) | Mixed-Polarity Multiple-Control Toffoli (MPMCT) gate |
| Keyword(3) | Nearest Neighbor Architecture (NNA) |
| Keyword(4) | |
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| 1st Author's Name | Atsushi Matsuo |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan University) |
| 2nd Author's Name | Wakaki Hattori |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan University) |
| 3rd Author's Name | Shigeru Yamashita |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan University) |
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| Speaker | Author-1 |
| Date Time | 2021-03-03 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2020-73, HWS2020-48 |
| Volume (vol) | vol.120 |
| Number (no) | no.400(VLD), no.401(HWS) |
| Page | p.31 |
| #Pages | 1 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
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