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| Paper Abstract and Keywords | ||
| Presentation | 2021-01-26 13:10 Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT)  VLD2020-62 CPSY2020-45 RECONF2020-81 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention. Design Space Exploration (DSE) in HLS tools is effective in improving the quality of the final circuit, but due to the huge search space, optimization algorithms have not been sufficiently compared and investigated to date. In this study, we investigate the effectiveness of Optuna, an hyperparameter optimization framework, whose effectiveness in DSE for HLS design has not yet been fully investigated. However, existing DSE frameworks have a tight coupling between the compilation flow and the optimization function. For this problem, we propose a Scala-based DSL and DSE framework that separates the algorithm specification from the hardware optimization setting. In the future, we will implement and evaluate the framework to identify effective optimization algorithms for the DSE. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | domain-specific language / high-level synthesis / design space exploration / FPGA / Scala / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 339, RECONF2020-81, pp. 131-136, Jan. 2021. | |
| Paper # | RECONF2020-81 | |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-62 CPSY2020-45 RECONF2020-81 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM |
| Conference Date | 2021-01-25 - 2021-01-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2021-01-CPSY-RECONF-VLD-ARC-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Automated architecture exploration on Scala-based hardware development environment |
| Sub Title (in English) | |
| Keyword(1) | domain-specific language |
| Keyword(2) | high-level synthesis |
| Keyword(3) | design space exploration |
| Keyword(4) | FPGA |
| Keyword(5) | Scala |
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| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryota Yamashita |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 2nd Author's Name | Daichi Teruya |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 3rd Author's Name | Hironori Nakajo |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
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| Speaker | Author-1 |
| Date Time | 2021-01-26 13:10:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2020-62, CPSY2020-45, RECONF2020-81 |
| Volume (vol) | vol.120 |
| Number (no) | no.337(VLD), no.338(CPSY), no.339(RECONF) |
| Page | pp.131-136 |
| #Pages | 6 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
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