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| Paper Abstract and Keywords | ||
| Presentation | 2021-01-25 17:35 High speed architectures of decimal counters Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.)  VLD2020-54 CPSY2020-37 RECONF2020-73 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed using BCD code and abacus number representations respectively, and the design results show that the abacus architecture can be mainly implemented by shifting operations. Previous studies have proposed the use of the abacus number representation in digital systems, proving that adders using the abacus number representation are extremely fast. We also present a new carry look ahead algorithm by which, the carries are stored in some inserting flip-flops and the high speed counters can be implemented. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | dicimal counter / abacus number / Binary coded decimal / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 337, VLD2020-54, pp. 85-89, Jan. 2021. | |
| Paper # | VLD2020-54 | |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-54 CPSY2020-37 RECONF2020-73 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM |
| Conference Date | 2021-01-25 - 2021-01-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2021-01-CPSY-RECONF-VLD-ARC-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High speed architectures of decimal counters |
| Sub Title (in English) | |
| Keyword(1) | dicimal counter |
| Keyword(2) | abacus number |
| Keyword(3) | Binary coded decimal |
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| 1st Author's Name | Shuhei Yanagawa |
| 1st Author's Affiliation | Gunma University (Gunma Univ.) |
| 2nd Author's Name | Yuuki Tanaka |
| 2nd Author's Affiliation | Gunma University (Gunma Univ.) |
| 3rd Author's Name | Shugang Wei |
| 3rd Author's Affiliation | Gunma University (Gunma Univ.) |
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| Speaker | Author-1 |
| Date Time | 2021-01-25 17:35:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2020-54, CPSY2020-37, RECONF2020-73 |
| Volume (vol) | vol.120 |
| Number (no) | no.337(VLD), no.338(CPSY), no.339(RECONF) |
| Page | pp.85-89 |
| #Pages | 5 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
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