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Paper Abstract and Keywords
Presentation 2021-01-25 15:15
A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA
Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) VLD2020-49 CPSY2020-32 RECONF2020-68
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performance. However, the computational complexity of these convolutional operations is enormous. Weinvestigate the resolution reduction of the input image as a method to reduce the costs (computation complexity andrequired buffer size) of CNN and discuss the trade-off between classification accuracy and resolution. We propose ahighly parallelized CNN accelerator in the horizontal, vertical and channel directions. The parallelism parameterizedin each direction is scalable to the input resolution. It provides hardware that maximizes computational and resourceefficiency depending on a given input image resolution. We found the accuracy decrease is small even if the inputresolution is lower than the standard resolution of2242in the model based on MobileNetV2. As an example, at1282resolutions, the model achieves 64.2% (Top-1) accuracy on ImageNet and computational costs are reduced to about1/3 for a 7.3% decrease compared to the standard resolution case. Also, we propose a highly parallelized high-speedCNN accelerator with resolution scalable. The accelerator with spatial-parallelism parameterized is scalable to theinput resolution. The scalability enables efficient computation on various circuit scales for each resolution. We haveimplemented a low-resolution CNN based on MobileNetV2 on an FPGA board. The inference speed achieves framesper second by 17.0 times compared with CPU.
Keyword (in Japanese) (See Japanese page) 
(in English) Convolutional Neural Networks / hardware accelerator / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 339, RECONF2020-68, pp. 58-62, Jan. 2021.
Paper # RECONF2020-68 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-49 CPSY2020-32 RECONF2020-68

Conference Information
Committee CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM  
Conference Date 2021-01-25 - 2021-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2021-01-CPSY-RECONF-VLD-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA 
Sub Title (in English)  
Keyword(1) Convolutional Neural Networks  
Keyword(2) hardware accelerator  
Keyword(3) FPGA  
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1st Author's Name Koki Sayama  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Akira Jinguji  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Naoto Soga  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
4th Author's Name Hiroki Nakahara  
4th Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2021-01-25 15:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2020-49, CPSY2020-32, RECONF2020-68 
Volume (vol) vol.120 
Number (no) no.337(VLD), no.338(CPSY), no.339(RECONF) 
Page pp.58-62 
#Pages
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 


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