Paper Abstract and Keywords |
Presentation |
2021-01-19 13:05
[Invited Talk]
Design of serializer/deserializer circuits for adiabatic quantum-flux-parametron circuits using delay-line clocking Yuki Hironaka, Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2020-17 Link to ES Tech. Rep. Archives: SCE2020-17 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An adiabatic quantum-flux-parametron (AQFP) circuit is an extremely low-power Josephson logic family. A novel clocking scheme of AQFP circuits, delay-line clocking, have been proposed to lower the latency of AQFP circuits. In this paper we designed serializer and deserializer (SerDes) circuits for AQFP circuits using delay-line clocking scheme. The SerDes circuits are based on single-flux-quantum (SFQ) shift registers that performs as serial/parallel converters and are utilized to AQFP circuits by using SFQ-AQFP interface circuits. In design of the deserializer circuit, the SFQ shift register is composed of SFQ-to-AQFP interface circuits itself to simplify the structure and is clocked by low-skew clocking using AQFP-to-SFQ interface circuits. SerDes circuits are designed as their SFQ clock signals are generated by AQFP excitation clock current so that the whole circuit composed of SerDes circuits and AQFP test circuit can be clocked by the single clock signal. A test circuit of SerDes circuits integrated with 8-to-3 encoder circuit was fabricated and tested in experiment, correct operation was obtained at 4 GHz clock frequency. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SerDes circuits / serializer / deserializer / adiabatic quantum-flux-parametron (AQFP) circuit / AQFP circuit / single-flux-quantum circuit / SFQ circuit / Josephson logic |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 313, SCE2020-17, pp. 1-6, Jan. 2021. |
Paper # |
SCE2020-17 |
Date of Issue |
2021-01-12 (SCE) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SCE2020-17 Link to ES Tech. Rep. Archives: SCE2020-17 |
Conference Information |
Committee |
SCE |
Conference Date |
2021-01-19 - 2021-01-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
|
Paper Information |
Registration To |
SCE |
Conference Code |
2021-01-SCE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design of serializer/deserializer circuits for adiabatic quantum-flux-parametron circuits using delay-line clocking |
Sub Title (in English) |
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Keyword(1) |
SerDes circuits |
Keyword(2) |
serializer |
Keyword(3) |
deserializer |
Keyword(4) |
adiabatic quantum-flux-parametron (AQFP) circuit |
Keyword(5) |
AQFP circuit |
Keyword(6) |
single-flux-quantum circuit |
Keyword(7) |
SFQ circuit |
Keyword(8) |
Josephson logic |
1st Author's Name |
Yuki Hironaka |
1st Author's Affiliation |
Yokohama National University (Yokohama Natl. Univ.) |
2nd Author's Name |
Taiki Yamae |
2nd Author's Affiliation |
Yokohama National University (Yokohama Natl. Univ.) |
3rd Author's Name |
Naoki Takeuchi |
3rd Author's Affiliation |
Yokohama National University (Yokohama Natl. Univ.) |
4th Author's Name |
Nobuyuki Yoshikawa |
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Yokohama National University (Yokohama Natl. Univ.) |
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Speaker |
Author-1 |
Date Time |
2021-01-19 13:05:00 |
Presentation Time |
25 minutes |
Registration for |
SCE |
Paper # |
SCE2020-17 |
Volume (vol) |
vol.120 |
Number (no) |
no.313 |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2021-01-12 (SCE) |