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Paper Abstract and Keywords
Presentation 2020-11-18 14:25
On-chip power supply noise monitoring for evaluation of multi-chip board power delivery networks
Daichi Nakagawa, Kazuki Yasuda, Masaru Mashiba, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univ) VLD2020-31 ICD2020-51 DC2020-51 RECONF2020-50
Abstract (in Japanese) (See Japanese page) 
(in English) In these days, information and communication technology has been evolving more and more, and hardware security has been increasingly important. No matter how theoretically secure cryptographic algorithms are, side channel attacks and hardware trojans that cause malfunction of devise or leakage of secret information are known as major threat in recent years. In this study, we aim to acquire a technology to detect the impedance change caused by hardware Trojan insertion or side channel attack. By using multiple on-chip monitors, power noise shapes on a power delivery network between chips were captured. Resistances on various sizes are inserted to power delivery network between two chips as a representation of hardware trojan, and comparison between power noise shape without resistance insertion and one with resistance insertion are evaluated.
Keyword (in Japanese) (See Japanese page) 
(in English) IoT / Multi-chip board / On-chip monitor / Side channel attack / Hardware Trojan / Impedance / Correlation Coeffcient / Power Noise  
Reference Info. IEICE Tech. Rep., vol. 120, no. 235, ICD2020-51, pp. 115-117, Nov. 2020.
Paper # ICD2020-51 
Date of Issue 2020-11-10 (VLD, ICD, DC, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-31 ICD2020-51 DC2020-51 RECONF2020-50

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2020-11-17 - 2020-11-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2020 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2020-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On-chip power supply noise monitoring for evaluation of multi-chip board power delivery networks 
Sub Title (in English)  
Keyword(1) IoT  
Keyword(2) Multi-chip board  
Keyword(3) On-chip monitor  
Keyword(4) Side channel attack  
Keyword(5) Hardware Trojan  
Keyword(6) Impedance  
Keyword(7) Correlation Coeffcient  
Keyword(8) Power Noise  
1st Author's Name Daichi Nakagawa  
1st Author's Affiliation Kobe University (Kobe Univ)
2nd Author's Name Kazuki Yasuda  
2nd Author's Affiliation Kobe University (Kobe Univ)
3rd Author's Name Masaru Mashiba  
3rd Author's Affiliation Kobe University (Kobe Univ)
4th Author's Name Kazuki Monta  
4th Author's Affiliation Kobe University (Kobe Univ)
5th Author's Name Takaaki Okidono  
5th Author's Affiliation Kobe University (Kobe Univ)
6th Author's Name Takuji Miki  
6th Author's Affiliation Kobe University (Kobe Univ)
7th Author's Name Makoto Nagata  
7th Author's Affiliation Kobe University (Kobe Univ)
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Speaker
Date Time 2020-11-18 14:25:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-VLD2020-31,IEICE-ICD2020-51,IEICE-DC2020-51,IEICE-RECONF2020-50 
Volume (vol) IEICE-120 
Number (no) no.234(VLD), no.235(ICD), no.236(DC), no.237(RECONF) 
Page pp.115-117 
#Pages IEICE-3 
Date of Issue IEICE-VLD-2020-11-10,IEICE-ICD-2020-11-10,IEICE-DC-2020-11-10,IEICE-RECONF-2020-11-10 


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