Paper Abstract and Keywords |
Presentation |
2020-11-17 14:25
Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits Ryosuke Matsuo, Shin-ichi Minato (Kyoto Univ) VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 Link to ES Tech. Rep. Archives: ICD2020-44 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-speed operation. Several researchers have studied a synthesis method based on the Binary Decision Diagram (BDD), as BDD-based optical logic circuits can take advantage of the light speed. However, a fundamental disadvantage of BDD-based
optical logic circuits is high power consumption. To address this issue, we propose a variable ordering algorithm for minimizing the power consumption. To the best of our knowledge, this is the first study of an optimization method of BDDs for optical logic
circuits. In this paper, we demonstrate that the power consumption largely depends on the variable order of a BDD; however, an optimization problem of finding the variable order to minimize the power consumption has large time complexity. To reduce the execution time, our algorithm utilizes an efficient reordering method based on adjacent variable swap. Experimental results using 10-input logic functions obtained by applying an LUT technology mapper to an ISCAS’85 c7552 benchmark circuit demonstrate that our algorithm can reduces the power consumption by an average of 30% within a reasonable amount of time
compared to the results of variable orders that minimize the number of nodes. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Optical logic circuit / Binary Decision Diagram (BDD) / Variable ordering / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 234, VLD2020-24, pp. 78-83, Nov. 2020. |
Paper # |
VLD2020-24 |
Date of Issue |
2020-11-10 (VLD, ICD, DC, RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 Link to ES Tech. Rep. Archives: ICD2020-44 |
Conference Information |
Committee |
VLD DC RECONF ICD IPSJ-SLDM |
Conference Date |
2020-11-17 - 2020-11-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2020 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2020-11-VLD-DC-RECONF-ICD-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits |
Sub Title (in English) |
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Optical logic circuit |
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Binary Decision Diagram (BDD) |
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Variable ordering |
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1st Author's Name |
Ryosuke Matsuo |
1st Author's Affiliation |
Kyoto University (Kyoto Univ) |
2nd Author's Name |
Shin-ichi Minato |
2nd Author's Affiliation |
Kyoto University (Kyoto Univ) |
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Speaker |
Author-1 |
Date Time |
2020-11-17 14:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2020-24, ICD2020-44, DC2020-44, RECONF2020-43 |
Volume (vol) |
vol.120 |
Number (no) |
no.234(VLD), no.235(ICD), no.236(DC), no.237(RECONF) |
Page |
pp.78-83 |
#Pages |
6 |
Date of Issue |
2020-11-10 (VLD, ICD, DC, RECONF) |
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