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| Presentation | 2020-10-26 17:40 Investigation of High-Efficiency Simulation Method for Detection of Physical Design Falsification in Secure IC Chip Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Makoto Nagata (Kobe Univ.)  HWS2020-41 ICD2020-30 Link to ES Tech. Rep. Archives: ICD2020-30 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the development of the IoT society in recent years, various security measures have been developed for integrated circuits in hardware. There is a concern that attackers may steal embedded information from malicious small circuits called hardware trojans. In this paper, we have developed a technique to detect unintentional design alteration such as hardware trojan in the design stage of an integrated circuit by simulation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Hardware trojan / Integrated circuit / Design alteration / Simulation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 212, ICD2020-30, pp. 94-98, Oct. 2020. | |
| Paper # | ICD2020-30 | |
| Date of Issue | 2020-10-19 (HWS, ICD) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | HWS2020-41 ICD2020-30 Link to ES Tech. Rep. Archives: ICD2020-30 |
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| Conference Information | |
| Committee | ICD HWS |
| Conference Date | 2020-10-26 - 2020-10-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2020-10-ICD-HWS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation of High-Efficiency Simulation Method for Detection of Physical Design Falsification in Secure IC Chip |
| Sub Title (in English) | |
| Keyword(1) | Hardware trojan |
| Keyword(2) | Integrated circuit |
| Keyword(3) | Design alteration |
| Keyword(4) | Simulation |
| Keyword(5) | |
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| 1st Author's Name | Kazuki Yasuda |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Kazuki Monta |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Daichi Nakagawa |
| 3rd Author's Affiliation | Kobe University (Kobe Univ.) |
| 4th Author's Name | Makoto Nagata |
| 4th Author's Affiliation | Kobe University (Kobe Univ.) |
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| Speaker | Author-1 |
| Date Time | 2020-10-26 17:40:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | HWS2020-41, ICD2020-30 |
| Volume (vol) | vol.120 |
| Number (no) | no.211(HWS), no.212(ICD) |
| Page | pp.94-98 |
| #Pages | 5 |
| Date of Issue | 2020-10-19 (HWS, ICD) |
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