Paper Abstract and Keywords |
Presentation |
2020-10-26 13:00
Design of Efficient AES Hardware with Immediately Fault Detection Capability Yusuke Yagyu, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2020-31 ICD2020-20 Link to ES Tech. Rep. Archives: ICD2020-20 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents an efficient AES encryption/decryption hardware architecture
with a fault detection scheme.
The proposed hardware detects fault(s) during encryption and decryption immediately, mainly to counter fault injection attacks with differential fault analysis (DFA).
The proposed hardware employs a fault detection scheme to verify the correctness and detect faults,
where the datapath is divided into two subblocks of linear and nonlinear parts,
and an inverse function is executed one clock after a half of round function.
The proposed hardware combines the above fault detection scheme with the state-of-the-art datapath optimization techniques (e.g., operation reordering, register retiming, and multiplicative-offset)
to achieve both efficient AES encryption/decryption and tamper-resistance to DFAs.
We show that the proposed AES hardware achieves 92% higher area-throughput efficiency and 47% lower power consumption than conventional hardware through a logic synthesis and simulation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
AES hardware architechure / fault injection attack / differential fault analysis / fault tolerance / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 211, HWS2020-31, pp. 36-41, Oct. 2020. |
Paper # |
HWS2020-31 |
Date of Issue |
2020-10-19 (HWS, ICD) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
HWS2020-31 ICD2020-20 Link to ES Tech. Rep. Archives: ICD2020-20 |
Conference Information |
Committee |
ICD HWS |
Conference Date |
2020-10-26 - 2020-10-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Hardware Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2020-10-ICD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design of Efficient AES Hardware with Immediately Fault Detection Capability |
Sub Title (in English) |
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Keyword(1) |
AES hardware architechure |
Keyword(2) |
fault injection attack |
Keyword(3) |
differential fault analysis |
Keyword(4) |
fault tolerance |
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1st Author's Name |
Yusuke Yagyu |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Rei Ueno |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Naofumi Homma |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2020-10-26 13:00:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
HWS2020-31, ICD2020-20 |
Volume (vol) |
vol.120 |
Number (no) |
no.211(HWS), no.212(ICD) |
Page |
pp.36-41 |
#Pages |
6 |
Date of Issue |
2020-10-19 (HWS, ICD) |
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