Paper Abstract and Keywords |
Presentation |
2020-10-26 09:25
Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2020-26 ICD2020-15 Link to ES Tech. Rep. Archives: ICD2020-15 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular multipliers are effective. Because processing on a pipelined implementation is more complex than without it, that has a potential of resistance against power analysis attack. However, the detailed analyses have not been studied enough. This report discusses the potential that an attacker extracts secret information by power analysis attack with adequate inputs focusing pipeline scheduling to the targeted pairing hardware. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
advanced cryptography / pairing hardware / pipeline scheduling / power analysis attack / side-channel security / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 211, HWS2020-26, pp. 7-12, Oct. 2020. |
Paper # |
HWS2020-26 |
Date of Issue |
2020-10-19 (HWS, ICD) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
HWS2020-26 ICD2020-15 Link to ES Tech. Rep. Archives: ICD2020-15 |
Conference Information |
Committee |
ICD HWS |
Conference Date |
2020-10-26 - 2020-10-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Hardware Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2020-10-ICD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware |
Sub Title (in English) |
|
Keyword(1) |
advanced cryptography |
Keyword(2) |
pairing hardware |
Keyword(3) |
pipeline scheduling |
Keyword(4) |
power analysis attack |
Keyword(5) |
side-channel security |
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1st Author's Name |
Mitsufumi Yamazaki |
1st Author's Affiliation |
Yokohama National University (YNU) |
2nd Author's Name |
Junichi Sakamoto |
2nd Author's Affiliation |
Yokohama National University (YNU) |
3rd Author's Name |
Tsutomu Matsumoto |
3rd Author's Affiliation |
Yokohama National University (YNU) |
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Speaker |
Author-1 |
Date Time |
2020-10-26 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
HWS2020-26, ICD2020-15 |
Volume (vol) |
vol.120 |
Number (no) |
no.211(HWS), no.212(ICD) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2020-10-19 (HWS, ICD) |
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