Paper Abstract and Keywords |
Presentation |
2020-10-26 09:00
Examination of requirements for power side-channel attack resistance evaluation boards of cryptographic integrated circuits
-- PDN transfer impedance contributing to leakage strength -- Tomonobu Kan, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) HWS2020-25 ICD2020-14 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
When evaluating the resistance of a cryptographic circuit to power analysis attacks by measurement, it is not easy to evaluate the IC alone, so the evaluation is performed by mounting the IC on the evaluation board. However, the evaluation board’s specifications are not defined, and even if the same IC is evaluated, the evaluation result may differ depending on the mounted evaluation board. Since it is not possible to determine which evaluation result is credible, it is necessary to unify the evaluation environment. In this study, we consider that side-channel information leakage depends on the transfer impedance, and the purpose is to determine the required specifications of the transfer impedance. In this paper, we show an example in which the evaluation results of side-channel attack resistance differ between the inside of the IC and the substrate, and confirm that the side-channel information leakage depends on the transmission impedance. Using two types of evaluation boards, SASEBO-G and SENPU, the correlation coefficient calculated from the SC leakage waveform measured at the measurement port on the evaluation board was about the same. SENPU, in contrast, had a larger correlation coefficient at the IC level that was calculated from the relational expression between SNR and the correlation coefficient. Comparing the amplitudes of the leaked waveforms, SASEBO-G was 18 times larger. We also calculated the transfer impedance based on the equivalent circuits of the power distribution networks of the FPGA core circuits of both boards. SASEBO-G was larger transfer impedances than SENPU. This result shows that the side-channel information leakage depends on the transfer impedance of the IC power distribution network. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Side-channel attack / Correlation power analysis / AES / Evaluation board / Signal to noise ratio (SNR) / Transfer impedance / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 211, HWS2020-25, pp. 1-6, Oct. 2020. |
Paper # |
HWS2020-25 |
Date of Issue |
2020-10-19 (HWS, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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HWS2020-25 ICD2020-14 |
Conference Information |
Committee |
ICD HWS |
Conference Date |
2020-10-26 - 2020-10-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Hardware Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2020-10-ICD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Examination of requirements for power side-channel attack resistance evaluation boards of cryptographic integrated circuits |
Sub Title (in English) |
PDN transfer impedance contributing to leakage strength |
Keyword(1) |
Side-channel attack |
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Correlation power analysis |
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AES |
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Evaluation board |
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Signal to noise ratio (SNR) |
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Transfer impedance |
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1st Author's Name |
Tomonobu Kan |
1st Author's Affiliation |
Okayama University (Okayama Univ.) |
2nd Author's Name |
Kengo Iokibe |
2nd Author's Affiliation |
Okayama University (Okayama Univ.) |
3rd Author's Name |
Yoshitaka Toyota |
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Okayama University (Okayama Univ.) |
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Speaker |
1 |
Date Time |
2020-10-26 09:00:00 |
Presentation Time |
25 |
Registration for |
HWS |
Paper # |
IEICE-HWS2020-25,IEICE-ICD2020-14 |
Volume (vol) |
IEICE-120 |
Number (no) |
no.211(HWS), no.212(ICD) |
Page |
pp.1-6 |
#Pages |
IEICE-6 |
Date of Issue |
IEICE-HWS-2020-10-19,IEICE-ICD-2020-10-19 |