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Paper Abstract and Keywords
Presentation 2020-10-22 10:50
High capacitance density high breakdown voltage textured deep trench SiN capacitors toward 3D integration
Koga Saito, Ayano Yoshida, Rihito Kuroda (Tohoku Univ.), Hiroshi Shibata, Taku Shibaguchi, Naoya kuriyama (LAPIS Semiconductor Miyagi), Shigetoshi Sugawa (Tohoku Univ.) SDM2020-15
Abstract (in Japanese) (See Japanese page) 
(in English) High capacitance density and High breakdown voltage textured deep trench SiN capacitors are presented. The developed capacitors achieved over 230fF/μm^2 capacitance density, 9.0V breakdown voltage and low leakage current. The capacitor has a structure that can be utilized for various compact electronic systems by using 3D integration technologies.
Keyword (in Japanese) (See Japanese page) 
(in English) Capacitor / High capacitance / High breakdown voltage / SiN / Textured deep trench / 3D integration / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 205, SDM2020-15, pp. 7-11, Oct. 2020.
Paper # SDM2020-15 
Date of Issue 2020-10-15 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM  
Conference Date 2020-10-22 - 2020-10-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process Science and New Process Technology 
Paper Information
Registration To SDM 
Conference Code 2020-10-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High capacitance density high breakdown voltage textured deep trench SiN capacitors toward 3D integration 
Sub Title (in English)  
Keyword(1) Capacitor  
Keyword(2) High capacitance  
Keyword(3) High breakdown voltage  
Keyword(4) SiN  
Keyword(5) Textured deep trench  
Keyword(6) 3D integration  
Keyword(7)  
Keyword(8)  
1st Author's Name Koga Saito  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Ayano Yoshida  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Rihito Kuroda  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Hiroshi Shibata  
4th Author's Affiliation LAPIS Semiconductor Miyagi Co.,Ltd. (LAPIS Semiconductor Miyagi)
5th Author's Name Taku Shibaguchi  
5th Author's Affiliation LAPIS Semiconductor Miyagi Co.,Ltd. (LAPIS Semiconductor Miyagi)
6th Author's Name Naoya kuriyama  
6th Author's Affiliation LAPIS Semiconductor Miyagi Co.,Ltd. (LAPIS Semiconductor Miyagi)
7th Author's Name Shigetoshi Sugawa  
7th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker
Date Time 2020-10-22 10:50:00 
Presentation Time 30 
Registration for SDM 
Paper # IEICE-SDM2020-15 
Volume (vol) IEICE-120 
Number (no) no.205 
Page pp.7-11 
#Pages IEICE-5 
Date of Issue IEICE-SDM-2020-10-15 


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