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| Presentation | 2020-09-11 14:55 An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech)  RECONF2020-27 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Convolutional neural networks(CNNs) are widely used for image tasks in both embedded systems and data centers. Particularly, when deploying CNNs in a data center, achieving high accuracy and low latency are important for various tasks. We propose an FPGA-based inference accelerator for randomly wired convolutional neural networks(RWCNNs), whose layer structures are based on random graph models. Because RWCNN can be processed in parallel, we can reduce the latency by concurrently using multiple computational units. We use the HBM2 to store feature maps, as multiple computational units need to simultaneously access different feature maps. In addition, the HBM channels and computational units are connected using a crossbar switch to efficiently transfer the feature maps. We allocate each layer to computational units using a simple heuristic algorithm. In addition, we allocate each layer to the HBM channels by coloring a conflict graph built based on the allocated schedule. This makes it possible for the computational units to access HBM channels in parallel. We implemented our accelerator on an Alveo U50 FPGA and compared it with a FPGA-based inference accelerator that targets ResNet-50. In the ImageNet image classification task, we could process an image in 16.6 ms, which is 43% lower than that for a conventional accelerator. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Deep Learning / CNN / FPGA / RWCNN / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 168, RECONF2020-27, pp. 48-53, Sept. 2020. | |
| Paper # | RECONF2020-27 | |
| Date of Issue | 2020-09-03 (RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2020-27 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2020-09-10 - 2020-09-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2020-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | CNN |
| Keyword(3) | FPGA |
| Keyword(4) | RWCNN |
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| 1st Author's Name | Ryosuke Kuramochi |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 2nd Author's Name | Hiroki Nakahara |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
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| Speaker | Author-1 |
| Date Time | 2020-09-11 14:55:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2020-27 |
| Volume (vol) | vol.120 |
| Number (no) | no.168 |
| Page | pp.48-53 |
| #Pages | 6 |
| Date of Issue | 2020-09-03 (RECONF) |
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