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Paper Abstract and Keywords
Presentation 2020-03-06 14:30
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
Abstract (in Japanese) (See Japanese page) 
(in English) In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semiconductor technologies, it is increasing in defects whose detection is difficult in testing using conventional fault models. One of such defects is modeled by resistive open fault model. Resistive open faults represent degradation in conductivity within circuit's interconnects and result in small delay faults that causing timing failures. Hence, it is important to generate test patterns consider longest possible path. The size of an additional delay at a resistive open fault is determined by the logic values at the adjacent lines and the length of the adjacent lines. Therefore, it is important to fault propagation paths and adjacent lines in test generation for resistive open faults. In this paper, we propose a test generation method for resistive open faults which considers fault propagation paths and the number of reversed phase transitions on adjacent lines using Partial MaxSAT. Moreover, we evaluate the generated test set using a fault simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) resistive open faults / Partial MaxSAT / test generation / adjacent lines / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 443, VLD2019-131, pp. 215-220, March 2020.
Paper # VLD2019-131 
Date of Issue 2020-02-26 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-131 HWS2019-104

Conference Information
Committee HWS VLD  
Conference Date 2020-03-04 - 2020-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2020-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver 
Sub Title (in English)  
Keyword(1) resistive open faults  
Keyword(2) Partial MaxSAT  
Keyword(3) test generation  
Keyword(4) adjacent lines  
1st Author's Name Hiroshi Yamazaki  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Yuta Ishiyama  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Tatsuma Matsuta  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Toshinori Hosokawa  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Masayoshi Yoshimura  
5th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
6th Author's Name Masayuki Arai  
6th Author's Affiliation Nihon University (Nihon Univ.)
7th Author's Name Hiroyuki Yotsuyanagi  
7th Author's Affiliation Tokushima University (Tokushima Univ.)
8th Author's Name Masaki Hashizume  
8th Author's Affiliation Tokushima University (Tokushima Univ.)
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Date Time 2020-03-06 14:30:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2019-131,IEICE-HWS2019-104 
Volume (vol) IEICE-119 
Number (no) no.443(VLD), no.444(HWS) 
Page pp.215-220 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2020-02-26,IEICE-HWS-2020-02-26 

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