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Paper Abstract and Keywords
Presentation 2020-03-06 13:00
Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit
Takumi Okamoto, Daisuke Fujimoto (NAIST), Kazuo Sakiyama, Li Yang (UEC), Yu-ichi Hayashi (NAIST) VLD2019-128 HWS2019-101
Abstract (in Japanese) (See Japanese page) 
(in English) Fault analysis for the cryptographic module is roughly divided into two phases; those are injecting transient faults and analysis of faulty outputs. In methods of injecting faults, especially clock glitches, have been frequently used in previous researches. This method has mainly focused on faults caused by setup time violations due to the combinational circuit delay. Since characteristics of faulty outputs due to setup time violations depends on the implementation of combination circuits, the suitable analysis methods for each faulty outputs were proposed. On the other hands, in this paper, we consider the faults caused by time violation on the input of sequential circuits and discuss the possibility of extracting secret keys from the faulty outputs. If the above fault analysis is feasible, we do not need to pay attention to the differences in implementation methods of combination circuits. Because the trend of faulty ciphertexts only depends on the input threshold of sequential circuits and the characteristic of signal rising and falling. In the experiment, after the proposed fault injection method applies to 3 different implementations of the Advanced Encryption Standard (AES), the same analysis method is used to each faulty outputs and demonstrated that a secret key could be extracted; the effectiveness of the proposed method will be shown.
Keyword (in Japanese) (See Japanese page) 
(in English) Fault Analysis / Sequential Circuit / Timing Violation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 444, HWS2019-101, pp. 197-201, March 2020.
Paper # HWS2019-101 
Date of Issue 2020-02-26 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee HWS VLD  
Conference Date 2020-03-04 - 2020-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2020-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit 
Sub Title (in English)  
Keyword(1) Fault Analysis  
Keyword(2) Sequential Circuit  
Keyword(3) Timing Violation  
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1st Author's Name Takumi Okamoto  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Daisuke Fujimoto  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Kazuo Sakiyama  
3rd Author's Affiliation The University of Electro- Communications (UEC)
4th Author's Name Li Yang  
4th Author's Affiliation The University of Electro- Communications (UEC)
5th Author's Name Yu-ichi Hayashi  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2020-03-06 13:00:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2019-128, HWS2019-101 
Volume (vol) vol.119 
Number (no) no.443(VLD), no.444(HWS) 
Page pp.197-201 
#Pages
Date of Issue 2020-02-26 (VLD, HWS) 


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