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Paper Abstract and Keywords
Presentation 2020-03-06 17:15
Circuit Architecture Exploration for Optical Neural Network based on Integrated Nanophotonics
Naoki Hattori, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.), Jun Shiomi (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT) VLD2019-137 HWS2019-110
Abstract (in Japanese) (See Japanese page) 
(in English) With a rapid progress of the integrated nanophotonics technology, optical neural networks
based on the integrated nanophotonics attract significant attention. This paper presents an optical neural network architecture which can perform inference processing at a speed of light. The architecture fully exploits optical parallelism of lights using wavelength division
multiplexing (WDM) in vector-matrix multiplication. The paper also presents a light-speed activation circuit based on nanophotonic O-E-O converter. Finally, using an intrusion detection system as an application, the paper explores appropriate circuit structures which can fully exploit ultra-low latency nature and optical parallelism of lights without degrading the inference accuracy.
Keyword (in Japanese) (See Japanese page) 
(in English) Optical Neural Network / Wavelength Division Multiplexing / Intrusion Detection System / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 443, VLD2019-137, pp. 251-256, March 2020.
Paper # VLD2019-137 
Date of Issue 2020-02-26 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-137 HWS2019-110

Conference Information
Committee HWS VLD  
Conference Date 2020-03-04 - 2020-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2020-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Circuit Architecture Exploration for Optical Neural Network based on Integrated Nanophotonics 
Sub Title (in English)  
Keyword(1) Optical Neural Network  
Keyword(2) Wavelength Division Multiplexing  
Keyword(3) Intrusion Detection System  
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1st Author's Name Naoki Hattori  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Yutaka Masuda  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Tohru Ishihara  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Jun Shiomi  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Akihiko Shinya  
5th Author's Affiliation NTT Nanophotonics Center (NTT)
6th Author's Name Masaya Notomi  
6th Author's Affiliation NTT Basic Research Center (NTT)
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Speaker
Date Time 2020-03-06 17:15:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2019-137,IEICE-HWS2019-110 
Volume (vol) IEICE-119 
Number (no) no.443(VLD), no.444(HWS) 
Page pp.251-256 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2020-02-26,IEICE-HWS-2020-02-26 


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