Paper Abstract and Keywords |
Presentation |
2020-03-05 11:20
stochasitc fast estimation of timing error induced circuit lifetime distribution Hazuki Tomiyama, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2019-113 HWS2019-86 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In VLSI design, a designer needs the integrated circuit to keep correct operation under area, power,
and performance constraints. For satisfying such constraints, a conventional logic simulator has been used. On the
other hand, due to recent continuous process minitualization, the logic simulator suffers from its slow computation
since the circuit tends to have larger scale and becomes complex. This paper proposes a stochastic simulator that
estimates the circuit lifetime which is denoted as the time when timing error occurs. Our proposed simulator focuses
on the important events, such as the activation of critical paths, and evaluates these events in a stochasitic way.
Thanks to the aggregation of events and these stochastic treatment, the number of event occurrent can be dramatically
reduced, which directly saves the computational time for lifetime estimation. This paper first implements
prototype of stochasitc simulator and compares the computational time and accuracy of lifetime estimation between
the prototype and logic simulator. Then, this work speeds up the prototype by further reducing the number of
events with Poisson process. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
circuit lifetime / logic simulator / stochastic simulator / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 443, VLD2019-113, pp. 113-118, March 2020. |
Paper # |
VLD2019-113 |
Date of Issue |
2020-02-26 (VLD, HWS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2019-113 HWS2019-86 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2020-03-04 - 2020-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Ken Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2020-03-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
stochasitc fast estimation of timing error induced circuit lifetime distribution |
Sub Title (in English) |
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Keyword(1) |
circuit lifetime |
Keyword(2) |
logic simulator |
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stochastic simulator |
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1st Author's Name |
Hazuki Tomiyama |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Yutaka Masuda |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Tohru Ishihara |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2020-03-05 11:20:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2019-113, HWS2019-86 |
Volume (vol) |
vol.119 |
Number (no) |
no.443(VLD), no.444(HWS) |
Page |
pp.113-118 |
#Pages |
6 |
Date of Issue |
2020-02-26 (VLD, HWS) |
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