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Paper Abstract and Keywords
Presentation 2020-03-03 09:40
A design and implementation of an HBM-based packet scheduler
Katsushi Kobayashi (U. Tokyo) SITE2019-94 IA2019-72
Abstract (in Japanese) (See Japanese page) 
(in English) Although only DRAM can realize buffer sizes required by packet schedulers in Internet routers, it is obvious that existing its bandwidth capacities cannot satisfy the bandwidths growth in the future.
High Bandwidth Memory (HBM) that significantly improves DRAM bandwidth throughputs by using silicon die stacking is emerging in the market.
This report presents a design and implementation of an HBM-based packet scheduler on FPGA.
Our HBM based scheduler implementation performed 75% of theoretical bandwidth of the HBM.
Keyword (in Japanese) (See Japanese page) 
(in English) Internet / Packet Scheduler / Memory Technology / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 435, IA2019-72, pp. 87-92, March 2020.
Paper # IA2019-72 
Date of Issue 2020-02-24 (SITE, IA) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee IA SITE IPSJ-IOT  
Conference Date 2020-03-02 - 2020-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Internet and Information Ethics Education, etc. 
Paper Information
Registration To IA 
Conference Code 2020-03-IA-SITE-IOT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A design and implementation of an HBM-based packet scheduler 
Sub Title (in English)  
Keyword(1) Internet  
Keyword(2) Packet Scheduler  
Keyword(3) Memory Technology  
1st Author's Name Katsushi Kobayashi  
1st Author's Affiliation The University of Tokyo (U. Tokyo)
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Date Time 2020-03-03 09:40:00 
Presentation Time 25 
Registration for IA 
Paper # IEICE-SITE2019-94,IEICE-IA2019-72 
Volume (vol) IEICE-119 
Number (no) no.434(SITE), no.435(IA) 
Page pp.87-92 
#Pages IEICE-6 
Date of Issue IEICE-SITE-2020-02-24,IEICE-IA-2020-02-24 

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