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Paper Abstract and Keywords
Presentation 2020-02-26 10:25
Defective Chip Prediction Modeling Using Convolutional Neural Networks
Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas) DC2019-87
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, the cost of LSI testing which guarantees reliability has relatively increased due to the development of high integration technology and lower prices. So far, method to defective prediction modeling for test cost reduction using data mining techniques such as machine learning has been proposed. This paper propose a method to improve the discrimination accuracy of defective prediction models by applying convolutional neural networks (CNN) which is one of the recent deep learning techniques. We expected to automate complicated data analysis and feature engineering with highly accurate defective prediction by utilizing the feature extraction structure of CNN. In addition, we investigate a new cost reduction method based on defective prediction considering yield rate. The effectiveness of the proposed method is shown by experimental results using actual manufacturing data.
Keyword (in Japanese) (See Japanese page) 
(in English) Data mining / LSI testing / Convolutional neural network / Defective prediction / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 420, DC2019-87, pp. 7-12, Feb. 2020.
Paper # DC2019-87 
Date of Issue 2020-02-19 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2020-02-26 - 2020-02-26 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To DC 
Conference Code 2020-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Defective Chip Prediction Modeling Using Convolutional Neural Networks 
Sub Title (in English)  
Keyword(1) Data mining  
Keyword(2) LSI testing  
Keyword(3) Convolutional neural network  
Keyword(4) Defective prediction  
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1st Author's Name Ryunosuke Oka  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satoshi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
3rd Author's Name Kouichi Kumaki  
3rd Author's Affiliation Renesas Electronics Corporation (Renesas)
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Speaker
Date Time 2020-02-26 10:25:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2019-87 
Volume (vol) IEICE-119 
Number (no) no.420 
Page pp.7-12 
#Pages IEICE-6 
Date of Issue IEICE-DC-2020-02-19 


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