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Paper Abstract and Keywords
Presentation 2020-01-30 13:10
[Invited Talk] A Proposal of MOS LSI Analog Sign-Off Verification.
Kimihiro Ogawa (Success Inc.) CAS2019-70 ICTSSL2019-39
Abstract (in Japanese) (See Japanese page) 
(in English) In analog MOS circuit sign-off verification to guarantee design yield, it is well known that analog oriented methodology is mandatory, different from digital sign-off. Especially, Fast/Slow metric for digital considering only Max/Min of Ids is not good enough for analog. However, in Japanese analog design, the traditional sign-off methodology based on digital is still widely used, therefore I guess analog sign-off sometimes has some problems such as over-spec or under-spec. In this presentation, I will show the drawbacks of digital sign-off and the recommended analog sign-off. I hope this will make a turning point for Japanese analog designers.
Keyword (in Japanese) (See Japanese page) 
(in English) MOS Analog Circuit / Sign-off / Fast/Slow Corner / Design Yield / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 400, CAS2019-70, pp. 35-41, Jan. 2020.
Paper # CAS2019-70 
Date of Issue 2020-01-23 (CAS, ICTSSL) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2019-70 ICTSSL2019-39

Conference Information
Committee ICTSSL CAS  
Conference Date 2020-01-30 - 2020-01-31 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2020-01-ICTSSL-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Proposal of MOS LSI Analog Sign-Off Verification. 
Sub Title (in English)  
Keyword(1) MOS Analog Circuit  
Keyword(2) Sign-off  
Keyword(3) Fast/Slow Corner  
Keyword(4) Design Yield  
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1st Author's Name Kimihiro Ogawa  
1st Author's Affiliation Success International Inc. (Success Inc.)
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Speaker
Date Time 2020-01-30 13:10:00 
Presentation Time 60 
Registration for CAS 
Paper # IEICE-CAS2019-70,IEICE-ICTSSL2019-39 
Volume (vol) IEICE-119 
Number (no) no.400(CAS), no.401(ICTSSL) 
Page pp.35-41 
#Pages IEICE-7 
Date of Issue IEICE-CAS-2020-01-23,IEICE-ICTSSL-2020-01-23 


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