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Paper Abstract and Keywords
Presentation 2020-01-24 14:45
Partial synthesis method based on Column-wise verification for integer multipliers
Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2019-89 CPSY2019-87 RECONF2019-79
Abstract (in Japanese) (See Japanese page) 
(in English) Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be logic synthesized from the large numbers of selections. By modeling the missing portions with Look Up Table (LUT), the synthesis and verification problem can be formulated as Quantified Boolean Formulae (QBF). Partial synthesis works well for non-arithmetic circuits, but for integer multipliers it works only if the target circuit and the specification model to be compared are structurally very close. If the target circuit and the specification model to be compared are not close, such as the cases where implementations are gate level and the specification is just arithmetic multiplication symbol, partial logic synthesis can only work up for 12 bits integer multipliers. The reason is that the method must spend most of the time on the equivalence checking of the two circuits and it is very time consuming if the structures are not similar. Now there are interests in synthesis and verification of large size multipliers such as in cryptography. In this paper, we tried to give an improved and proposed method based on the traditional partial synthesis to speed up the process of large integer multipliers. We applied an approach named Column Wise method to do the last step of equivalence checking. The result showed that we can apply our method to 64 bits integer multipliers within 43 seconds.
Keyword (in Japanese) (See Japanese page) 
(in English) Partial synthesis / Column-wise / Integer multipliers / Gröbner basis / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 371, VLD2019-89, pp. 211-216, Jan. 2020.
Paper # VLD2019-89 
Date of Issue 2020-01-15 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF VLD2019-89 CPSY2019-87 RECONF2019-79

Conference Information
Committee IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC  
Conference Date 2020-01-22 - 2020-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2020-01-SLDM-RECONF-VLD-CPSY-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Partial synthesis method based on Column-wise verification for integer multipliers 
Sub Title (in English)  
Keyword(1) Partial synthesis  
Keyword(2) Column-wise  
Keyword(3) Integer multipliers  
Keyword(4) Gröbner basis  
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1st Author's Name Jian Gu  
1st Author's Affiliation the University of Tokyo (UTokyo)
2nd Author's Name Amir Masoud Gharehbaghi  
2nd Author's Affiliation the University of Tokyo (UTokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation the University of Tokyo (UTokyo)
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Speaker
Date Time 2020-01-24 14:45:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2019-89,IEICE-CPSY2019-87,IEICE-RECONF2019-79 
Volume (vol) IEICE-119 
Number (no) no.371(VLD), no.372(CPSY), no.373(RECONF) 
Page pp.211-216 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2020-01-15,IEICE-CPSY-2020-01-15,IEICE-RECONF-2020-01-15 


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