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| Presentation | 2020-01-23 11:50 Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.)  VLD2019-71 CPSY2019-69 RECONF2019-61 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction set architecture, where several CPU designs are provided under BSD licenses. Binary synthesis, a variant of high-level synthesis, can auto-generate hardware from assembly programs or inline assembly codes, and can be used to synthesize interrupt handler written in assebmly language into hardware. This article presents the first binary synthesizer which takes an executable binary codes for RV32IM and synthesizes a hardware module which is functionally equivalent with a CPU that runs the code. A CDFG is generated from a linked executable binary code, from which an RTL description is generated by the conventional high-level synthesis flow. This method can incorporate custum instructions into the synthesis flow, provided they are executed in fixed cycles and the execution units for them are separately designed from the CPU's datapath. From small scale codes consisting of less than 160 instructions, a prototype synthesizer has generated smaller and faster hardware modules than a Rocket Chip. A code containing SIMD add-saturate instruction has been also synthesized to accelerate the resulting hardware. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Binary synthesis / High-level synthesis / RISC-V / Hardware/Software codesign / Embedded systems / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 371, VLD2019-71, pp. 111-115, Jan. 2020. | |
| Paper # | VLD2019-71 | |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2019-71 CPSY2019-69 RECONF2019-61 |
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| Conference Information | |
| Committee | IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC |
| Conference Date | 2020-01-22 - 2020-01-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2020-01-SLDM-RECONF-VLD-CPSY-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Binary Synthesis from RISC-V Executables |
| Sub Title (in English) | |
| Keyword(1) | Binary synthesis |
| Keyword(2) | High-level synthesis |
| Keyword(3) | RISC-V |
| Keyword(4) | Hardware/Software codesign |
| Keyword(5) | Embedded systems |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shoki Hamana |
| 1st Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
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| Speaker | Author-1 |
| Date Time | 2020-01-23 11:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2019-71, CPSY2019-69, RECONF2019-61 |
| Volume (vol) | vol.119 |
| Number (no) | no.371(VLD), no.372(CPSY), no.373(RECONF) |
| Page | pp.111-115 |
| #Pages | 5 |
| Date of Issue | 2020-01-15 (VLD, CPSY, RECONF) |
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