Paper Abstract and Keywords |
Presentation |
2020-01-22 11:50
DDR4 SDRAM controller for real-time processing So Haramura, Nobuyuki Yamasaki (Keio Univ.) VLD2019-56 CPSY2019-54 RECONF2019-46 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, larger scale programs are frequently used in embedded systems, and a higher capacity of main memory is required. Besides, current semiconductor manufacturing technology has realized DRAM power savings, lower prices, and higher capacities. Therefore, high capacity DRAM is widely used as main memory in embedded devices. However, the gap between memory and processor speed is increasing, there is the memory wall problem that the access latency to the memory increases. The worst case execution time of the task will increase, and the time predictability of the task decreases. Furthermore, if time predictability decreases, high grained task execution should be impossible. In this paper, we proposed a prioritized real-time DDR4 SDRAM controller to improve the high priority tasks performance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
DDR4 / real-time / DRAM controller / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 373, RECONF2019-46, pp. 13-17, Jan. 2020. |
Paper # |
RECONF2019-46 |
Date of Issue |
2020-01-15 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2019-56 CPSY2019-54 RECONF2019-46 |
Conference Information |
Committee |
IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC |
Conference Date |
2020-01-22 - 2020-01-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Raiosha, Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2020-01-SLDM-RECONF-VLD-CPSY-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
DDR4 SDRAM controller for real-time processing |
Sub Title (in English) |
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DDR4 |
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real-time |
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DRAM controller |
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1st Author's Name |
So Haramura |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Nobuyuki Yamasaki |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2020-01-22 11:50:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2019-56, CPSY2019-54, RECONF2019-46 |
Volume (vol) |
vol.119 |
Number (no) |
no.371(VLD), no.372(CPSY), no.373(RECONF) |
Page |
pp.13-17 |
#Pages |
5 |
Date of Issue |
2020-01-15 (VLD, CPSY, RECONF) |
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