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Paper Abstract and Keywords
Presentation 2019-12-23 16:20
InP Wafer-level Backside Process for Future Tera-hertz Operation
Takuya Tsutsumi, Hiroshi Hamada, Hiroki Sugiyama, Hideyuki Nosaka, Hideaki Matsuzaki (NTT) ED2019-82
Abstract (in Japanese) (See Japanese page) 
(in English) The sub-millimeter-wave band would be utilized in future mobile networks to cope with increasing data rates. InP-based SMMIC (Submillimeter-wave monolithic ICs) have attracted much attention because InP-based transistors feature superior RF characteristics. This paper reports wafer-level backside process technology consists of thinning a 3-inch InP wafer, forming dense vias, backside metalization with single-level wiring. We also applied the developed backside bias-lines to an actual SMMIC in order to enhance IC layout effectiveness and reduce electric loss of the RF signals. Finally, we successfully demonstrate a power amplifier with the world’s highest level output power of +9.5 dBm up to the 300-GHz range without any degradation of transistor characteristics.
Keyword (in Japanese) (See Japanese page) 
(in English) SubmiIIimeter-wave monolithic ICs (SMMICs) / Indium phosphide (InP) / (InP),Wafer-level backside process / backside lines / High electron mobility transistors (HEMTs) / Heterojunction bipolar transistors (HBTs) / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 353, ED2019-82, pp. 23-28, Dec. 2019.
Paper # ED2019-82 
Date of Issue 2019-12-16 (ED) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ED THz  
Conference Date 2019-12-23 - 2019-12-24 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ED 
Conference Code 2019-12-ED-THz 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) InP Wafer-level Backside Process for Future Tera-hertz Operation 
Sub Title (in English)  
Keyword(1) SubmiIIimeter-wave monolithic ICs (SMMICs)  
Keyword(2) Indium phosphide (InP)  
Keyword(3) (InP),Wafer-level backside process  
Keyword(4) backside lines  
Keyword(5) High electron mobility transistors (HEMTs)  
Keyword(6) Heterojunction bipolar transistors (HBTs)  
1st Author's Name Takuya Tsutsumi  
1st Author's Affiliation Nippon Telegraph and Telephone Corp. (NTT)
2nd Author's Name Hiroshi Hamada  
2nd Author's Affiliation Nippon Telegraph and Telephone Corp. (NTT)
3rd Author's Name Hiroki Sugiyama  
3rd Author's Affiliation Nippon Telegraph and Telephone Corp. (NTT)
4th Author's Name Hideyuki Nosaka  
4th Author's Affiliation Nippon Telegraph and Telephone Corp. (NTT)
5th Author's Name Hideaki Matsuzaki  
5th Author's Affiliation Nippon Telegraph and Telephone Corp. (NTT)
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Date Time 2019-12-23 16:20:00 
Presentation Time 25 
Registration for ED 
Paper # IEICE-ED2019-82 
Volume (vol) IEICE-119 
Number (no) no.353 
Page pp.23-28 
#Pages IEICE-6 
Date of Issue IEICE-ED-2019-12-16 

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