Paper Abstract and Keywords |
Presentation |
2019-11-15 16:10
Low Latency Interrupt Handling Scheme By Using Interrupt Wake-Up Mechanism Ryo Wada, Nobuyuki Yamasaki (Keio Univ.) CPSY2019-50 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, embedded real-time systems used in spacecraft and automobiles have become increasingly complex and are required to be able to handle both periodic and aperiodic tasks. When an interrupt occurs, the program counter generally shifts to the corresponding exception vector and systems incur large overhead due to context switching.
In this paper, we design and implement a software mechanism to reduce the interrupt response time for improving system reliability and demonstrate the effectiveness of our proposed method by RTL simulations.
The evaluation results show that our proposed method achieves high real-time performance by reducing the interrupt response time by up to 88% compared to the existing interrupt processing. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Embedded Real-Time System / SMT / Interruption / Interrupt Wake-Up / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 286, CPSY2019-50, pp. 71-76, Nov. 2019. |
Paper # |
CPSY2019-50 |
Date of Issue |
2019-11-07 (CPSY) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2019-50 |
Conference Information |
Committee |
VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB |
Conference Date |
2019-11-13 - 2019-11-15 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ehime Prefecture Gender Equality Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2019 -New Field of VLSI Design- |
Paper Information |
Registration To |
CPSY |
Conference Code |
2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Low Latency Interrupt Handling Scheme By Using Interrupt Wake-Up Mechanism |
Sub Title (in English) |
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Keyword(1) |
Embedded Real-Time System |
Keyword(2) |
SMT |
Keyword(3) |
Interruption |
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Interrupt Wake-Up |
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1st Author's Name |
Ryo Wada |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Nobuyuki Yamasaki |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2019-11-15 16:10:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2019-50 |
Volume (vol) |
vol.119 |
Number (no) |
no.286 |
Page |
pp.71-76 |
#Pages |
6 |
Date of Issue |
2019-11-07 (CPSY) |