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| Presentation | 2019-11-14 15:05 Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks Tomoki Chiba, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)  ICD2019-32 IE2019-38 Link to ES Tech. Rep. Archives: ICD2019-32 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose a design of a computational unit for multiply-accumulate (MAC) operations and activation functions utilizing a next-generation nonvolatile memory device for binarized neural network hardware. The proposed circuit reduces the memory access cost by embedding nonvolatile memory devices into logic cells. In addition, the proposed circuit performs the accumulation and activation functions at once by a new circuit configuration based on current-mode linear summation. Through an experimental evaluation of the proposed circuit, we show the impact of the proposed design scheme on compact and energy-efficient neural network hardware. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | binarized neural networks / nonvolatile memory / XNOR / bitcounting / variation compensation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 284, ICD2019-32, pp. 19-24, Nov. 2019. | |
| Paper # | ICD2019-32 | |
| Date of Issue | 2019-11-07 (ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2019-32 IE2019-38 Link to ES Tech. Rep. Archives: ICD2019-32 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB |
| Conference Date | 2019-11-13 - 2019-11-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ehime Prefecture Gender Equality Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2019 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks |
| Sub Title (in English) | |
| Keyword(1) | binarized neural networks |
| Keyword(2) | nonvolatile memory |
| Keyword(3) | XNOR |
| Keyword(4) | bitcounting |
| Keyword(5) | variation compensation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tomoki Chiba |
| 1st Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 2nd Author's Name | Masanori Natsui |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Takahiro Hanyu |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2019-11-14 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2019-32, IE2019-38 |
| Volume (vol) | vol.119 |
| Number (no) | no.284(ICD), no.285(IE) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2019-11-07 (ICD, IE) |
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