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Paper Abstract and Keywords
Presentation 2019-11-14 15:20
A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs
Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67
Abstract (in Japanese) (See Japanese page) 
(in English) One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability and to maintain the high fault efficiency. To solve the challenge, a design-for-testability method for a stuck-at-faults using partial scan design and controller augmentation to execute the operations of easily testable functional k-time expansion models was proposed. In the partial scan design, state registers in controllers are replaced with scan registers. As the results, test generation is freely able to transfer to any invalid states of controllers by shifting operations. High fault efficiency was achieved by designing state transitions of invalid states such that hardware elements in a data-path circuits become testable. In this paper, we propose a method to generate easily testable functional k-time expansion models for transition faults based on the conventional design-for-testability method to reduce the area overhead and test application time and to maintain fault efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) Easily testable functional k-time expansion models / Controller augmentation / Partial scan design / k-cycle capture testing / Transition faults / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 283, DC2019-67, pp. 133-138, Nov. 2019.
Paper # DC2019-67 
Date of Issue 2019-11-06 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-43 DC2019-67

Conference Information
Committee VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB 
Conference Date 2019-11-13 - 2019-11-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Ehime Prefecture Gender Equality Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2019 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs 
Sub Title (in English)  
Keyword(1) Easily testable functional k-time expansion models  
Keyword(2) Controller augmentation  
Keyword(3) Partial scan design  
Keyword(4) k-cycle capture testing  
Keyword(5) Transition faults  
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1st Author's Name Yuta Ishiyama  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Yuki Ikegaya  
3rd Author's Affiliation Nihon University (Nihon Univ.)
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Speaker
Date Time 2019-11-14 15:20:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-VLD2019-43,IEICE-DC2019-67 
Volume (vol) IEICE-119 
Number (no) no.282(VLD), no.283(DC) 
Page pp.133-138 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2019-11-06,IEICE-DC-2019-11-06 


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