講演抄録/キーワード |
講演名 |
2019-11-13 11:20
A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults ○Peikun Wang・Amir Masaud Gharehbaghi・Masahiro Fujita(The Univ. of Tokyo) VLD2019-32 DC2019-56 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
In this paper, we propose a new ATPG-based logic optimization method by removing the redundant multiple faults. In order to find the redundant multiple faults, the incremental ATPG method is applied to quickly filter out the non-redundant faults. The multiple redundancies are eliminated from higher cardinality to lower cardinality; and hence, more redundancies can be removed. The experimental results up to redundant triple faults indicate that the proposed method can remove more redundancy comparing to the redundancy removal command in the synthesis tool SIS. |
キーワード |
(和) |
/ / / / / / / |
(英) |
logic optimization / redundant multiple faults / incremental fault selection method / / / / / |
文献情報 |
信学技報, vol. 119, no. 282, VLD2019-32, pp. 19-22, 2019年11月. |
資料番号 |
VLD2019-32 |
発行日 |
2019-11-06 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2019-32 DC2019-56 |
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