Paper Abstract and Keywords |
Presentation |
2019-09-20 10:40
Multi-threaded High-Level Synthesis for Bandwidth-intensive Applications Jens Huthmann, Auter Podobas, Takaaki Miyajima, Atsushi Koshiba, Kentaro Sano (RIKEN) RECONF2019-30 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Using stream computing on Field-Programmable Gate Arrays (FPGAs) has in the recent decades shown promise for practical and performance-effective deployment of reconfigurable architecture in High-Performance Computers (HPC). The stream computing paradigm remedies (in parts) the classical von-Neumann bottleneck, while the FPGA provides a malleable computationa l substrate much needed to cater to the different applications. Often a simple Direct Memory Access (DMA) is used to stream data from the memory subsystem through the FPGA. This works well for as long as data is regu larly (preferably linearly) layed-out in the external memory - a feature that that is not always the case.
In this work, we show our preliminary work in replacing the inflexi ble Direct Memory Access (DMA) with a highly specialized, multi-threaded , memory-access front-end. By exploiting thread-level parallelism to com bine and expose memory access from multiple context, we aspire to utiliz e the available memory bandwidth better than what would otherwise be pos sible. We show our initial results on the StreamCopy benchmark, where we show that our multi-threaded memory front-end achieves up to 61.5% of p eak bandwidth, which is comparable performance to a dedicated DMA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-Level Synthesis / Memory Bandwidth / Multi-threading / / / Stratix 10 / FPGA / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 208, RECONF2019-30, pp. 51-56, Sept. 2019. |
Paper # |
RECONF2019-30 |
Date of Issue |
2019-09-12 (RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2019-30 |
Conference Information |
Committee |
RECONF |
Conference Date |
2019-09-19 - 2019-09-20 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
KITAKYUSHU Convention Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2019-09-RECONF |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Multi-threaded High-Level Synthesis for Bandwidth-intensive Applications |
Sub Title (in English) |
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Keyword(1) |
High-Level Synthesis |
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Memory Bandwidth |
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Multi-threading |
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Keyword(6) |
Stratix 10 |
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FPGA |
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1st Author's Name |
Jens Huthmann |
1st Author's Affiliation |
RIKEN (RIKEN) |
2nd Author's Name |
Auter Podobas |
2nd Author's Affiliation |
RIKEN (RIKEN) |
3rd Author's Name |
Takaaki Miyajima |
3rd Author's Affiliation |
RIKEN (RIKEN) |
4th Author's Name |
Atsushi Koshiba |
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RIKEN (RIKEN) |
5th Author's Name |
Kentaro Sano |
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RIKEN (RIKEN) |
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Speaker |
Author-1 |
Date Time |
2019-09-20 10:40:00 |
Presentation Time |
20 minutes |
Registration for |
RECONF |
Paper # |
RECONF2019-30 |
Volume (vol) |
vol.119 |
Number (no) |
no.208 |
Page |
pp.51-56 |
#Pages |
6 |
Date of Issue |
2019-09-12 (RECONF) |
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