Paper Abstract and Keywords |
Presentation |
2019-08-07 13:30
[Invited Talk]
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1 Link to ES Tech. Rep. Archives: SDM2019-36 ICD2019-1 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The main feature of this processor is its inter-chip connection interface for making a larger chip. A credit card sized compute node integrating two CMOS-APs was also developed as an interface with existing computer systems. The compute node can handle up to 61,952 spins at a time. A performance evaluation using the node improved the CPU speed by 55 times in solving a minimum vertex cover problem, one of the NP-hard combinatorial optimization problems. Finally, we describe a cloud interface for the compute node to make the CMOS-APs more useful and to promote application development for it. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Combinatorial optimization / Annealing / Accelerator / Ising model / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 161, SDM2019-36, pp. 1-5, Aug. 2019. |
Paper # |
SDM2019-36 |
Date of Issue |
2019-07-31 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2019-36 ICD2019-1 Link to ES Tech. Rep. Archives: SDM2019-36 ICD2019-1 |
Conference Information |
Committee |
SDM ICD ITE-IST |
Conference Date |
2019-08-07 - 2019-08-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Univ., Graduate School /Faculty of Information Science and |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
Paper Information |
Registration To |
SDM |
Conference Code |
2019-08-SDM-ICD-IST |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems |
Sub Title (in English) |
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Keyword(1) |
Combinatorial optimization |
Keyword(2) |
Annealing |
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Accelerator |
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Ising model |
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1st Author's Name |
Masato Hayashi |
1st Author's Affiliation |
Hitachi, Ltd. (Hitachi) |
2nd Author's Name |
Takashi Takemoto |
2nd Author's Affiliation |
Hitachi, Ltd. (Hitachi) |
3rd Author's Name |
Chihiro Yoshimura |
3rd Author's Affiliation |
Hitachi, Ltd. (Hitachi) |
4th Author's Name |
Masanao Yamaoka |
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Hitachi, Ltd. (Hitachi) |
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Speaker |
Author-1 |
Date Time |
2019-08-07 13:30:00 |
Presentation Time |
45 minutes |
Registration for |
SDM |
Paper # |
SDM2019-36, ICD2019-1 |
Volume (vol) |
vol.119 |
Number (no) |
no.161(SDM), no.162(ICD) |
Page |
pp.1-5 |
#Pages |
5 |
Date of Issue |
2019-07-31 (SDM, ICD) |
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