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Paper Abstract and Keywords
Presentation 2019-07-24 14:10
Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset
Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the proposed architectures employ a new trick for optimizing construction of linear operations named multiplicative-offset, in addition to register-retiming and operation-reordering techniques. As a result of logic syntheses, we confirm that the proposed AES encryption/decryption hardware and encryption hardware achieve approximately 51–57% and 58–64% higher efficiency than conventional ones, respectively
Keyword (in Japanese) (See Japanese page) 
(in English) AES / Hardware architectures / Round-based encryption datapath / unified encryption/decryption architecture / CBC mode / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 143, HWS2019-53, pp. 375-382, July 2019.
Paper # HWS2019-53 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee ISEC SITE ICSS EMM HWS BioX IPSJ-CSEC IPSJ-SPT 
Conference Date 2019-07-23 - 2019-07-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi University of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset 
Sub Title (in English)  
Keyword(1) AES  
Keyword(2) Hardware architectures  
Keyword(3) Round-based encryption datapath  
Keyword(4) unified encryption/decryption architecture  
Keyword(5) CBC mode  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Rei Ueno  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Sumio Morioka  
2nd Author's Affiliation Interstellar Technologies Inc. (IST)
3rd Author's Name Noriyuki Miura  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Kohei Matsuda  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Makoto Nagata  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Shivam Bhasin  
6th Author's Affiliation Nanyang Technological University (NTU)
7th Author's Name Yves Mathieu  
7th Author's Affiliation Telecom ParisTech (TPT)
8th Author's Name Tarik Graba  
8th Author's Affiliation Telecom ParisTech (TPT)
9th Author's Name Jean-Luc Danger  
9th Author's Affiliation Telecom ParisTech (TPT)
10th Author's Name Naofumi Homma  
10th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker
Date Time 2019-07-24 14:10:00 
Presentation Time 25 
Registration for HWS 
Paper # IEICE-ISEC2019-58,IEICE-SITE2019-52,IEICE-BioX2019-50,IEICE-HWS2019-53,IEICE-ICSS2019-56,IEICE-EMM2019-61 
Volume (vol) IEICE-119 
Number (no) no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) 
Page pp.375-382 
#Pages IEICE-8 
Date of Issue IEICE-ISEC-2019-07-16,IEICE-SITE-2019-07-16,IEICE-BioX-2019-07-16,IEICE-HWS-2019-07-16,IEICE-ICSS-2019-07-16,IEICE-EMM-2019-07-16 


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