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Paper Abstract and Keywords
Presentation 2019-07-23 13:10
A Formal Approach to Verifying Trojan-freeness of Cryptographic Circuits Based on Galois-Field Arithmetic
Akira Ito, Rei Ueno, Naofumi Homma (Tohoku Univ.) ISEC2019-26 SITE2019-20 BioX2019-18 HWS2019-21 ICSS2019-24 EMM2019-29
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a formal method for verifying whether Hardware Trojan (HT) exists or not (i.e., HT-freeness) in cryptographic hardware. The proposed method focuses on GF arithmetic circuits which are commonly used for a major part of modern cryptographic hardware. Since the functionality of GF arithmetic circuits can be given by a set of GF equations, the proposed method detects the existence of HTs or verifies HT-freeness by checking the equivalence between GF equations (i.e., circuit specification) and flattened gate-level netlist of a target circuit. In the proposed method, we first derive GF equations (i.e., circuit specification) over a representation of Boolean polynomial ring using the zero-suppressed binary decision diagram (ZDD). We then construct the ZDD representation of the target netlist, and finally check whether or not the two ZDDs are isomorphic, which make it possible to perform an efficient and complete HT-freeness verification. In this paper, we demonstrate the highest efficiency of the proposed method through the experimental verification of GF multipliers with various input length including practical ones used in elliptic curve cryptography, and 128-bit AES hardware datapath.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Trojan detection / Galois-field circuits / Formal verification / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 143, HWS2019-21, pp. 133-138, July 2019.
Paper # HWS2019-21 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2019-26 SITE2019-20 BioX2019-18 HWS2019-21 ICSS2019-24 EMM2019-29

Conference Information
Committee ISEC SITE ICSS EMM HWS BioX IPSJ-CSEC IPSJ-SPT 
Conference Date 2019-07-23 - 2019-07-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi University of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Formal Approach to Verifying Trojan-freeness of Cryptographic Circuits Based on Galois-Field Arithmetic 
Sub Title (in English)  
Keyword(1) Hardware Trojan detection  
Keyword(2) Galois-field circuits  
Keyword(3) Formal verification  
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1st Author's Name Akira Ito  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Rei Ueno  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Naofumi Homma  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2019-07-23 13:10:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # ISEC2019-26, SITE2019-20, BioX2019-18, HWS2019-21, ICSS2019-24, EMM2019-29 
Volume (vol) vol.119 
Number (no) no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) 
Page pp.133-138 
#Pages
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 


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