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| Presentation | 2019-05-17 11:00 [Invited Talk] Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology (from DSD 2018) Jean-Luc Danger (Telecom ParisTech), Risa Yashiro (UEC), Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet (Telecom ParisTech), Kazuo Sakiyama (UEC), Noriyuki Miura, Makoto Nagata (Kobe University), Sylvain Guilley (Secure-IC)  ISEC2019-3 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this talk, we introduce the paper “Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology” by Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata, Sylvain Guilley, which was presented at DSD 2018 held in Prague, Czech Republic from August 29 to 31, 2018. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | PUF / TRNG / FD-SOI / analysis / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 40, ISEC2019-3, pp. 5-5, May 2019. | |
| Paper # | ISEC2019-3 | |
| Date of Issue | 2019-05-10 (ISEC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ISEC2019-3 |
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| Conference Information | |
| Committee | ISEC |
| Conference Date | 2019-05-17 - 2019-05-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ISEC |
| Conference Code | 2019-05-ISEC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology (from DSD 2018) |
| Sub Title (in English) | |
| Keyword(1) | PUF |
| Keyword(2) | TRNG |
| Keyword(3) | FD-SOI |
| Keyword(4) | analysis |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Jean-Luc Danger |
| 1st Author's Affiliation | Telecom ParisTech (Telecom ParisTech) |
| 2nd Author's Name | Risa Yashiro |
| 2nd Author's Affiliation | The University of Electro-Communications (UEC) |
| 3rd Author's Name | Tarik Graba |
| 3rd Author's Affiliation | Telecom ParisTech (Telecom ParisTech) |
| 4th Author's Name | Yves Mathieu |
| 4th Author's Affiliation | Telecom ParisTech (Telecom ParisTech) |
| 5th Author's Name | Abdelmalek Si-Merabet |
| 5th Author's Affiliation | Telecom ParisTech (Telecom ParisTech) |
| 6th Author's Name | Kazuo Sakiyama |
| 6th Author's Affiliation | The University of Electro-Communications (UEC) |
| 7th Author's Name | Noriyuki Miura |
| 7th Author's Affiliation | Kobe University (Kobe University) |
| 8th Author's Name | Makoto Nagata |
| 8th Author's Affiliation | Kobe University (Kobe University) |
| 9th Author's Name | Sylvain Guilley |
| 9th Author's Affiliation | Secure-IC (Secure-IC) |
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| Speaker | Author-2 |
| Date Time | 2019-05-17 11:00:00 |
| Presentation Time | 30 minutes |
| Registration for | ISEC |
| Paper # | ISEC2019-3 |
| Volume (vol) | vol.119 |
| Number (no) | no.40 |
| Page | p.5 |
| #Pages | 1 |
| Date of Issue | 2019-05-10 (ISEC) |
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