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Paper Abstract and Keywords
Presentation 2019-05-10 10:00
An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2019-10
Abstract (in Japanese) (See Japanese page) 
(in English) Since the convolutional neural network has a high-performance recognition accuracy,
it is expected to implement various applications on an embedded vision system.
An FPGA can calculate the inference algorithm with low-latency and low power consumption using a specific circuit.

In the paper, we propose a quantized weights with weight pruning, to reduce the operation cost and parameters of PSPNet.
We set 8-bit precision for CNN weights and activations using a linear quantization to reduce circuit area.
And we prune wasteful weights to reduce MACs and weights parameters.
We apply an indirect memory access architecture to skip zero part and propose the weight parallel 2D convolutional circuit.
It can be applied to the AlexNet based CNN, which has different size kernels.
Thus, we design the AlexNet based PSPNet to reduce the number of layers toward low-latency computation.
In the experiment, by applying the proposed scheme, it reduces the 93% of weight parameter.
We implement the proposed PSPNet on a Xilinx zcu102 evaluation board, by using Xilinx SDSoC 2018.2.2.
It archived 79.0 frames per second (FPS) on self-driving dataset.
Compared with single path CNN, it was 14.0% times higher accuracy.
In terms of its over-head of the hardware area,
it requires 1.08 times BRAMs, 1.38 times DSPs, 2.30 times FFs and 1.67 times LUTs.
Keyword (in Japanese) (See Japanese page) 
(in English) Convolutional Neural Network / FPGA / Semantic Segmentation / Quantization / Pruning / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 18, RECONF2019-10, pp. 49-54, May 2019.
Paper # RECONF2019-10 
Date of Issue 2019-05-02 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2019-10

Conference Information
Committee RECONF  
Conference Date 2019-05-09 - 2019-05-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokyo Tech Front 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable system, etc. 
Paper Information
Registration To RECONF 
Conference Code 2019-05-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure 
Sub Title (in English)  
Keyword(1) Convolutional Neural Network  
Keyword(2) FPGA  
Keyword(3) Semantic Segmentation  
Keyword(4) Quantization  
Keyword(5) Pruning  
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Keyword(8)  
1st Author's Name Youki Sada  
1st Author's Affiliation Tokyo Institute of Technology (titech)
2nd Author's Name Masayuki Shimoda  
2nd Author's Affiliation Tokyo Institute of Technology (titech)
3rd Author's Name Shimpei Sato  
3rd Author's Affiliation Tokyo Institute of Technology (titech)
4th Author's Name Hiroki Nakahara  
4th Author's Affiliation Tokyo Institute of Technology (titech)
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Speaker Author-1 
Date Time 2019-05-10 10:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2019-10 
Volume (vol) vol.119 
Number (no) no.18 
Page pp.49-54 
#Pages
Date of Issue 2019-05-02 (RECONF) 


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